In my full chip design I have multiple IO pad groups, one regular IO, 2 pairs of Oscillator IO with their corresponding supplies, A pair of analog VD, VS Pad. The VSSIO ring is common to all these pads for ESD purpose. The VDDIO, VDD, VSS power rail for each group were given different names ( like VDD1, VDD2, VDDIO1 etc). In LVS the connectivity is not matched. The FX mismatch says that the particualr power nets of each IO pads are connected to some nets with different numbers ( 3456 etc) instead of VDD1 or VDDIO1 or VSSIO). I can see that both the layout and source has the nets, but the layout names corrsponds to some numbers rather than the net name. How can I solve this?
Also there are ESD diodes for all these Pads which is being reported as unmatched instance. Please help me solve the issue.