I've found that the maximum skew between DQ signals and their corresponding DQS must be less than 5ps for ddr3-1066(I'm simulating a board with xilinx FPGA and this is what it's needed for virtex-6). now I have three questions:

1- what is the definition of the skew between DQ and DQS?

2- how can I achieve this? I mean simulating the board in hyperlynx, and setting the probe to the die, is only the first step. then I simulate every single DQ net in a bytelane and the corresponding DQS. Is it correct to simulate single DQ and then load them altogether to view their skew?

3- if it's correct, how can I achieve +/- 5ps? I mean the rise and fall time of each individual DQ is not the same, so de-skewing the waveforms in their rising edges will result another skew in the falling edge which is greater than +/-5 ps.

really appreciate any answer.

hai

The memory controller will move the Data (DQ) signals by synchronising with Differential Data Strobes (DQS), which in turn tracks the System Clock

to measure the skew select all the data byte lines corresponding to a data strobe and simulate by assigning the transmitter and receiver model and save the wave forms of all the data byte lines corresponding to adata strobe one by one

load all the waveforms in the oscilloscope and measure the skew ,but what is the allowable skew is available in the controller fpga data sheets in various terms ddr wizard wiil validate the skew on individual lines and provide pass or fail report

to achieve your tolerance match the length of the data lines with the strobe lines

select symmetric impedance stack up ,in ddr routed layers

try to route the similar data lane (group) and skew in same layer with same number of vias

if routed in different layer compentiate layer stub

variation in stub length on top will create skew as the propagation delay is not equal in external and internal layers

regards

AGXIN.J