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How to import verilog to pyxis schmeatic

Question asked by robbyku13 on Nov 28, 2014
Latest reply on Nov 30, 2017 by vilas

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hi everyone,

I want to ask about import verilog file into pyxis schematic. When I try to import pyxis need map file, what is map file?. Because I dont have map file just verilog file,

is there someone who can help me?

I use : pyxis v10.2, design kit :HK_C35, and calibre : 2012.2_17

thanks

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lpalocko Dec 5, 2014 3:56 PM
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hi,

what kind of verilog file do you have? You need verilog file which is created after synthesis (for example export from leonardo spectrum). You can not use verilog files which are written at behavioral level of abstraction. Then you need 'tmf file' which contain a list of standard cells.

Regards,

Lukas
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ron_tinnell Dec 5, 2014 5:14 PM
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Hello,

There are two was to use Verilog with the Pyxis tools.
1. If you import the Verilog with the Pyxis Project Manager, then the file is copied into your project. For each module in the Verilog, a cell with the corresponding module name is created in a project library. The model is compiled for use with the Questa simulator and a symbol in generated.
2. Import Verilog with Pyxis Schematic. This approach will generate schematics. The Verilog must be behavioral Verilog and not RTL.
It appears you are doing #2. The file required maps the primitive Verilog elements to Pyxis symbols. You need to use the "Create Template Mapping File" button on the dialog first. This file then needs to be modified so that all of the primitives have a path to the corresponding symbol that will be used on the generated schematics. Search for the topic "About Schematic Creation from a Verilog Netlist" in the Pyxis Schematic User's Manual.

Regards,
Ron

1. Browse for your Verilog or enter the path under the Netlist Files: section of the dialog box
2. After pressing the "Create Template Mapping File..." button, the following dialog should appear. Click the "Edit" button and update the mapping file.
3. After editing and saving the mapping file, press OK on the dialog above and the Import Verilog dialog will fill in the path to the mapping file.
4. Enter a directory (library) where you want the schematics to be placed and click OK.
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ron_tinnell @ ron_tinnell on Jan 11, 2015 7:03 PM
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Hello Lukas,

If you believe this correctly resolves your question, then please mark the answer as correct.

Thanks,
Ron
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vilas @ ron_tinnell on Nov 30, 2017 7:57 AM
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Hello Ron

We want for (digital) IC layout design, from the leonardo generated verilog netlist .
We followed the procedure outline, created the v_tmp files, and also the entered the name of "Output Directory"
After this , when we hit "OK", the following error message is generated.
Any help in this regards will be appreciated. Thank you.

Best Regards
Razak
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robbyku13 Mar 16, 2015 2:15 AM
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thanks ron_tinnell i will try
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How to import verilog to pyxis schmeatic

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