5 Replies Latest reply on Nov 30, 2017 7:57 AM by vilas

    How to import verilog to pyxis schmeatic

    robbyku13
    robbyku13 Nov 28, 2014 1:30 AM

      hi everyone,

       

      I want to ask about import verilog file into pyxis schematic. When I try to import pyxis need map file, what is map file?. Because I dont have map file just verilog file,

       

      is there someone who can help me?

       

      I use : pyxis v10.2, design kit :HK_C35, and calibre : 2012.2_17

      thanks

       

        • 1. Re: How to import verilog to pyxis schmeatic
          lpalocko
          lpalocko Dec 5, 2014 3:56 PM (in response to robbyku13)

          hi,

           

          what kind of verilog file do you have? You need verilog file which is created after synthesis (for example export from leonardo spectrum). You can not use verilog files which are written at behavioral level of abstraction. Then you need 'tmf file' which contain a list of standard cells.

           

          Regards,

           

          Lukas

          • 2. Re: How to import verilog to pyxis schmeatic
            ron_tinnell
            ron_tinnell Dec 5, 2014 5:14 PM (in response to robbyku13)

            Hello,

             

            There are two was to use Verilog with the Pyxis tools.

             

            1. If you import the Verilog with the Pyxis Project Manager, then the file is copied into your project. For each module in the Verilog, a cell with the corresponding module name is created in a project library. The model is compiled for use with the Questa simulator and a symbol in generated.
            2. Import Verilog with Pyxis Schematic. This approach will generate schematics. The Verilog must be behavioral Verilog and not RTL.

             

            It appears you are doing #2. The file required maps the primitive Verilog elements to Pyxis symbols. You need to use the "Create Template Mapping File" button on the dialog first. This file then needs to be modified so that all of the primitives have a path to the corresponding symbol that will be used on the generated schematics. Search for the topic "About Schematic Creation from a Verilog Netlist" in the Pyxis Schematic User's Manual.

             

             

            Regards,

            Ron

             

            1. Browse for your Verilog or enter the path under the Netlist Files: section of the dialog box

            ImportVerilog1.jpeg

            2. After pressing the "Create Template Mapping File..." button, the following dialog should appear. Click the "Edit" button and update the mapping file.

            ImportVerilog2.jpeg

            3. After editing and saving the mapping file, press OK on the dialog above and the Import Verilog dialog will fill in the path to the mapping file.

            ImportVerilog3.jpeg

            4. Enter a directory (library) where you want the schematics to be placed and click OK.

            1 of 1 people found this helpful
            • 3. Re: How to import verilog to pyxis schmeatic
              ron_tinnell
              ron_tinnell Jan 11, 2015 7:03 PM (in response to ron_tinnell)

              Hello Lukas,

               

              If you believe this correctly resolves your question, then please mark the answer as correct.

               

              Thanks,

              Ron

              • 4. Re: How to import verilog to pyxis schmeatic
                robbyku13
                robbyku13 Mar 16, 2015 2:15 AM (in response to robbyku13)

                thanks ron_tinnell i will try 

                • 5. Re: How to import verilog to pyxis schmeatic
                  vilas
                  vilas Nov 30, 2017 7:57 AM (in response to ron_tinnell)

                  Hello Ron

                   

                  We want for (digital) IC layout design, from the leonardo generated  verilog netlist .

                  We followed the procedure outline, created the v_tmp files, and also the entered the name of  "Output Directory"

                  After this , when we hit "OK", the following error message is generated.

                  Any help in this regards will be appreciated. Thank you.

                   

                  Best Regards

                  Razak