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DDR4 CLK/ADD/CMD and Control Termination in UDIMM EBD model

Question asked by hungreohd on Dec 12, 2017
Latest reply on Jan 2, 2018 by hungreohd

Dear everyone,

I use UDIMM EBD model to run the DDR4 timing in Hyperlynx Boardsim.

In the UDIMM EBD model, there is the important note below:

I had checked in the UDIMM EBD model. 36ohm resistors was already in .EBD file but there is lack of 0.01uF cap.

I don't know how to add the 0.01uF cap and connect to VDD pin in the UDIMM EBD model.

Similar with ADD/CMD and Control signals, I also want to terminate them to VTT as block diagram below:

I attached UDIMM EBD model for double check.

Thank you so much.

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