I've run a DC drop simulation with Hyperlynx PI on a PCB. Since the max load is nearly 50A, I placed a lot of vias (>100) for the current to go from the source to inner layers than to the sink. The simulations shows the current is not evenly distributed among the vias although all vias are the same. Several vias carry as much as 1.9A while the vast majority carry much less. Why is that? Is something wrong with the simulation or with my layout?