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uvm_hdl_force doesn't always work correctly in Questa

Question asked by hal9e3 on Mar 26, 2018

I've been using uvm_hdl_force on other signals in my VHDL design no problem. However, my latest attempt doesn't work correctly. Here's the signal declaration in a VHDL module:

 

signal clk0_div1 : integer := 0;

 

and here's the force command:

 

 

uvm_hdl_force("tb_top.dut.u_cnr.GEN_PLLS.u_MMCME3_adv_1.clk0_div1", 32'h0000000D);

 

The force works, it just sets it to 1, regardless of whether I use the above, 'hD, 13 or 'd13. The signal is inside a module that is instantiated using a GENERATE so I would understand if it just flat didn't work, but it's acting like the signal is a bit. Any ideas on why this isn't working?

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