9 Replies Latest reply on Apr 23, 2018 6:53 AM by weston_beal

    SPICE DDR 4 - INTEL FILES

    syedzaid

      We Seek Support from  Any One who has  Worked On the Spice Files For Intel SKYlake Processor.

      Of The buffer  Models provided, Which One will be the relevant one for the DD4.

       

      BUFFER_INTEL.JPG

        • 1. Re: SPICE DDR 4 - INTEL FILES
          weston_beal

          Unfortunately, you are unlikely to get the answer you need in this forum. The question should really be asked of Intel. On the other hand, it's not too hard to read through the top-level SPICE netlist and track down to the level where it instantiates the driver model. That way, you can be sure which file and which subcircuit is used in the version of the SI kit that you are working with.

           

          After you have found the file and subcircuit that you want to work with, we can help you connect it to an IBIS model for easy reuse in HyperLynx SI.

           

          Regards,

          Weston

          • 2. Re: SPICE DDR 4 - INTEL FILES
            syedzaid

            weston,

            Thanks For your Response.

             

            On Discussion with the other Team . we have received the Following response?

            Can you help us decode the Spice usage on to mentor Environment?

            -------------------------------------------------------------------------

            1.INC folder contains all the models needed like buffer, DIMM, package etc. These files are called in system deck SP file.

            2. below is sample example on the Subckt calls in one of the spice system deck. As it can be seen, driver_10line.inc is buffer model used while Vin_pattern.inc & input_pwl_step.inc are input patterns while fir2tap_xx.inc is called for FIR inclusion.

             

             

            ********** buffer & input stimulus file *****************************

             

            .include '../inc/buffer/vin_pattern.inc'            *$ input patterns

            .include '../inc/buffer/input_pwl_step.inc'         *$ input patterns

            .include '../inc/buffer/fir2tap_13003a.inc'         *$ x7tapfir1

            .include '../inc/buffer/driver_10line.inc'          *$ Bessel2, ix

            *************************************************************

            3. Spice system decks are the ones used for running simulations. You can provide the deck to Mentor and ask them to simulate instead of calling each model.

            -----------------------------------------------------

             

            If required I can Have the model shared ?

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            • 3. Re: SPICE DDR 4 - INTEL FILES
              weston_beal

              Syed,

               

              I am working with a very similar kit, so I have seen many of these same files. Here are some notes to help you along.

              • You can ignore the input pattern files. We create the stimulus pattern within HyperLynx SI.
              • The driver_10line.inc file is simply a subcircuit that instantiates 10 subcircuits of the actual driver. Go one step deeper to find the driver.
              • That driver model is not complete. You need to connect it with the subcircuit defined in fir2tap_13003a.inc. Also, the top-level circuit probably adds and RC at that die pad. The RC should be connected to the driver subcircuit.

              I suggest that you build a new subcircuit that connects the actual driver, the fir2tap and the pad RC. That full driver buffer subcircuit can be wrapped in IBIS with an External Model block, and then the IBIS buffer model can be used like any other common IBIS buffer model.

              https://support.mentor.com/knowledge-base/MG588513

               

              Regards,

              Weston

              • 4. Re: SPICE DDR 4 - INTEL FILES
                syedzaid

                Weston,

                 

                Thank-you for the brief and In-depth highlight for the Approach.

                1. If I get you right then we need to use all the Buffer models as seen the 1st image ?

                2. What is the role of SPICE Dec .sp Files In the Entire simulation ? are these Files even used for Simulation in the hyperlynx environment?

                3. To create the stimulus pattern do we need any other file other than the two buffer models as you mentioned?

                4. Bottom line , the answer I'm looking for is to the following question . ----- > are the files sufficient to run the simulation? do we need the ASIC vendor to Provide us with more Information ?

                5. IS there any document or reference that will help us use these spice files in the hyperlynx environment?

                 

                We Thank you for your support, and awaiting for a response.!

                • 5. Re: SPICE DDR 4 - INTEL FILES
                  weston_beal

                  Syed,

                   

                  1. If I get you right then we need to use all the Buffer models as seen the 1st image?

                       No, some of them are just combining 10 copies of actual buffer models. Some of them are just input stimuli that you should set up in HyperLynx.

                  2. What is the role of SPICE Dec .sp Files In the Entire simulation ? are these Files even used for Simulation in the HyperLynx environment?

                       Those are the complete circuit netlist and simulation options. Most of that should be set up in HyperLynx.

                  3. To create the stimulus pattern do we need any other file other than the two buffer models as you mentioned?

                       You should understand the stimulus created by the vendor-supplied files, and then recreate that pattern in HyperLynx.

                  4. Bottom line, the answer I'm looking for is to the following question. ----- > are the files sufficient to run the simulation? do we need the ASIC vendor to Provide us with more Information?

                       All the information you need is contained the supplied files. You just need to understand the SPICE syntax well enough to find out what the SPICE file defines for stimulus, netlist, and results.

                  5. IS there any document or reference that will help us use these spice files in the HyperLynx environment?

                       The article I reference before is a good starting place. There is additional information in the HyperLynx User Guide and in the IBIS specification describing [External Model].

                   

                  Regards,

                  Weston

                  1 of 1 people found this helpful
                  • 6. Re: SPICE DDR 4 - INTEL FILES
                    syedzaid

                    Weaston ,

                     

                    Thank you for providing us the clarity on the questions asked .

                    can we use the same Buffer models  driver_10line.inc and fir2tap .inc for all DDR Signals ( address , Dq, Clock and control signals ) ?

                     

                    • 7. Re: SPICE DDR 4 - INTEL FILES
                      weston_beal

                      Syed,

                       

                      You should _not_ use driver_10line.inc. This is just 10 copies of the pin driver. You should look in this file to see what subcircuit is used for each driver.

                      This is where you need to be able to read the SPICE syntax to find how the driver model is created, and which subcircuits are used in each case. There are probably different models for DQS, DQ, CLK and CA.

                       

                      Regards,

                      Weston

                      • 8. Re: SPICE DDR 4 - INTEL FILES
                        syedzaid

                        Weston,

                        What do you mean by different models ?

                        For DQS , DQ, CLK and CA- can the details be extracted from the Buffer Models Shared ?

                        If We Get you right , the Details of the Sub-circuit can be attained by decoding the Spice Syntax and the Same Can Be done For the Other signals in the same Buffer Model?

                        • 9. Re: SPICE DDR 4 - INTEL FILES
                          weston_beal

                          The driver models for DQS, DQ, CLK and CA are probably the same topology, but with different parameter values.

                          You just need to read through the SPICE netlist and find the specific data.

                           

                          Regards,

                          Weston