When I have seen this error, the problem is usually fairly obvious when I look into the details. Sometimes the inductor pin is not physically connected to the rest of the net or vias don't connect to the layers where they are needed. If the layout was done in Allegro then when you run the translation, you should select the 2 checkboxes to include detailed data for power integrity analysis. If you don't find the cause of the error pretty soon, I suggest submitting an SR on Support Center with the design data included. It is most likely a design-specific problem.
Thanks for the suggestion.
As the problem is not present in other projects we're investigating whether there are relevant differences between this project and the others. We've found that the input files are missing a drill layer, meaning that the problem could indeed be what you're describing.
I'll post an update as soon as I get new input files.