I'm running an HL simulation (HyperLynx SI/PI/Thermal VX.2.4_Update 1) of a PCIe Gen 2 link running across a VPX backplane. It does not seem to take the via stubs into account, and I want to know if I'm doing something wrong. The link is (relatively) simple: exit the IC on a surface layer, go through a resistor (standing in for the DC blocking cap needed in PCIe), to a via to an internal layer. Then route to the VPX connector pair, onto the backplane, and over to another VPX connector pair, on the same internal layer (same stackup as the daughter cards), onto an internal layer on the daughter card, to a via to the surface layer and into the receiver IC.
For the sake of this test, assume an 0.093" thick PWB, 8 layers, arranged as top-GND-signal2-GND-GND-signal3-GND-bottom, with 5 mils between each layer except the two center GNDs, which are about 55 mils apart.
I would expect a smaller eye diagram if the "inner layer" is signal2(layer 3), than if it were signal3(layer 6), due to the longer via stubs at the vias and also at the VPX connectors (through-hole connectors). But a simulation actually shows the opposite, routing on signal2 gives a (slightly) better eye than routing on signal3.
I am using the S-parameter model for the VPX connector provided by the vendor (TE Connectivity). I'm not doing 3D EM modeling for the vias (which could be part of the answer), but how do I take the connector via stubs into account? There are four connector stubs (two at each mated pair, one on the daughter card and one on the backplane), so they will be a larger contribution than the two surface-to-inner layer vias.