may be you should you try gate level extraction, with spef as output.
Hi. It's not possible to generate a gate-level calibreview. You can only generate a gate-level netlist in batch mode. What type of mixed-signal simulation are you doing, and what format is your digital block in?
Thanks for your response.
The digital block is a verilog netlist with SDF. I want to run an Analog Mixed Signal simulation with all the analog sub-blocks extracted individually. The digital sub block timing with be back annotated using the SDF file. I extract the top level interconnect and use that. In essence I retain one level of hierarchy while including parasitics at the top level. I need a calibreview just so I can run the AMS simulation.
I already tried doing this with a top level extracted calibre view. Simulations did not make progress for more than 24hrs. I think it could not handle the vast number of parasitics. Hence this approach.
Currently I have a set of sims running with a lot of manual modification of the top level calibre view. I am trying to see if I can make the process more automated.
I dont think i can use a SPEF output in my AMS simulation. Hence trying for calibre view. I am doing a gate level extraction at this point.
Hi Aarathy. Which simulation tool are you using? If you are using Mentor's ADVance MS, it would be better to use the Calibre xRC to ADMS integration, bypassing the calibreview. If you are using Virtuoso AMS Designer, it would be best to open a service request with Mentor Graphics support, and ask for an ehnhancement request for Calibre xRC's calibreview to do gate-level extraction.