How to deal with the AC capacitor in a serial link?

Bruce,

It's very simple to use spice model in HL. The model file you posted is for Cadence' s Allegro SI(DML format), but you can copy it's content and save as a .sp file to use in HL.Then, inn  free-from schematic, add a package/connetor instance on your chain and RMB the package/connector instance, click the library path button,add the directory where the .sp file stays. Now everything is ok.

Again, I hope you call Dr. You for better understanding how to do simulation if you live in China

Yanfeng

Hi Bruce,

One of your quesitons was "I'm really confused by the AC capacitor in a serial link, who can detail its function?"

This capacitor serves to remove the DC component that results from an un-even number of 1's and 0's in the bit stream from the AC signal so it switches around 0V.  Here's an article from Howard Johnson that you might find useful in explaining why you need them:

http://www.sigcon.com/Pubs/news/4_15.htm

The tricky part for simulation is that these capacitors have an RC time constant and they don't charge up instantly.  When they're in the actual hardware, they charge up seemingly fast (a few miliseconds). The problem is, in simulation, you typically don't simulate out to a few miliseconds, you're simulating a few nano-seconds, or if you're really patient, maybe microseconds.  So that means that your signal in simulation always looks bad unless you skip thousands of bits of simulation data.  The alternative is to use a SPICE capacitor model and set an initial condition on the nodes of the capacitor so that it is effectively charged right from the beginning. 

-Steve

I

Yes. Pepople should set the initial voltage to the cap.

Yanfeng

Hi Qin,

Dr. You is one of best freinds. He worked as Mentor TME and leaved months ago. Now Dr. You is in SERF, a Hyperlynx distributor in China. Here is the contact info. He normally stays in Beijing.

Yanfeng

深圳市瑟孚电子有限公司
SERF Electronics Co., Ltd
广东省深圳市南山区科苑北路清华信息港综合楼809室 邮编：518057
电话:0755-26030094
传真:0755-26030879
E-mail:sales@serf-eda.com

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E-mail:lifu_you@serf-eda.com

Generally speaking, you should take an approach to simulation just like any other engineering task.  Most designers don't have the time/bandwidth to be a research scientist.  You're job is to design a product and do it quickly, making engineering trade-offs along the way to optimize for cost, manufacturing, quality, and reliability. 

Translated to simulation, it's important to get the first order effects in your simulation to see the quality of your design - things like driver/receiver impedance, switching speeds, trace impedance, etc.  Then you come to second order effects, tolerancing of your stackup and trace geometry for manufacturing, having a more detailed model of components in your system (such as an AC cap).  Then you could go to third order effects, things that will have a minimal impact on the design, such as whether a via stub is going to cause you problem for signals that are running 3 Gbps or less (in this case, if the signal were 10 Gbps, that via might actually become a 1st order effect depending on board thickness and stub length).

In other words, if you run the simulation with a simple capacitor model rather than the complex distributed one that you initially posted, and you have plenty of margin on your signal, then you should feel confident that even with a more complex model, you'll still have plenty of margin (i.e. you don't need the complex model).  If you had very little margin on your signal though when you look at the first order effects, it becomes more important to pay attention to the 2nd order and in that case you may want to use a more advanced model for the capacitor.  In general though, for an AC cap, a simple model is sufficient.

I use to have a VHDL-AMS model of a fast charging cap somewhere that I will try to dig up and post to this thread. You could use this in your simulation and it should set the initial condition correctly.

-Steve

Attached is the fast charging VHDL-AMS model that I talked about.  You'll need to run the Compile.bat file in the zip, then open the FFS and run a simulation.  You'll see that the VHDL-AMS cap charges with 1 timestep where as the regular cap takes much more time to charge.

-Steve

Are you using HyperLynx 8.0?  I can send you an updated version of this that should run without running the compile on the models.

Can you also use a SPICE model with an initial condition in BoardSim?  I am currently evaluating HyperLynx, specifically for a PCI Express crosstalk issue.  I have not found a satisfactory way to deal with the AC capacitors, and I haven't found a way to use a SPICE model for the capacitor.

Thanks,

Andy

The issue I've found with the SPICE model is that it requires more than just an IC statement on the capacitor node.  You also need to add at UIC (Use Initial Conditions) on the .TRAN line of the SPICE simulation.  The IC statement alone only helps a SPICE engine converge on a DC solution, it doesn't have any impact on the transient simulation. However, because of the way HyperLynx works with ADMS, you can't edit the .TRAN line in your HyperLynx simulation.

This VHDL-AMS model is a good work around for this situation.  It essentially looks like a SPICE model to HyperLynx.  You can open the blackbox in the example schematic and then click Edit model and it will show you this SPICE SUBCKT:

.SUBCKT  Fast_C_wr  PortP  PortN
*====================================================
.model FastSettling_C(ideal) macro lang=VHDLAMS lib=CompiledLib
YfastC FastSettling_C(ideal)
+ generic:  Cval       = 10.0e-12
+           C0         = 1.00e-18
+           SwitchTime = 0.01e-9
+ port:     PortP  PortN
*====================================================
.ENDS
*====================================================

You can change the value of the capacitor here as well as the switching time of the capacitor (i.e. make it charge up faster than 10ps).

I've included an updated version of this so you should just be able to open the FFS and run it (no need to run any of the .bat files).  If this doesn't work for you, please let me know.  I ran it on my system and it seem to run OK with the native ADMS in HyperLynx v8.0 though - so you shouldn't experience any problems.  Below, you can see the fast charging cap will charge in 1 timestep vs the regular cap.

We have a good application note on SupportNet dealing with this issue.

http://supportnet.mentor.com/reference/appnotes/index.cfm?id=10828

My prefered method is to use a small resistor in place of the capacitor. It has the same high-frequency effect, but without the long charging time of the large series capacitor.

Weston