I am afraid that the wording of the poll does not make good of use of this opportunity. The only way that Placement and/or Setting up Constraints will out score Routing is if after one sets thing up, then one only autoroutes and does not do any cleanup. I believe that I do more pre-planning in the part placement and routing setup than most people that I have worked with, but the routing and routing clean-up still dominates the timeline. Maybe a percentage of time for each section would yield more information.
As "strangd" says the granularity on this one is a bit coarse.
I would note that since I am also often doing the front end design and schematics then prepairing for layout can be 200% or more than the layout time.
However in terms of PCB alone:
Prepairing for layout i.e. footprints (decals) and getting everthing to match plus ensuring properties e.g geometry.hight are in place. Up to 5%
Setting up constraints c. 1 % (typical), would be more on a high speed board.
Placement: 20% to 50% - IMHO placement is the key activity in any layout.
Power Plane Design: 5 to 10% I really try to maximising the number of sections per plane with the aim to minimise the number of layers needed and improve routability. Many of my board are mixed signal so I have seperate analog and digital arears plus the twidly bits in the power supply sections, particually if they are switchers.
Routing: Almost never more than 50%, and often a lot less. PADS Router gets used for diff pairs and length matching, pretty much everything else is done by hand in Layout. (PADS Router is a lot better these days, but it still doesn't have a [_] Pernickety check box.)
Layout reviews etc: perhaps 2% to 5%
Documentation: 2% (ish) Putting in boarders, sorting out sheet numbers, making the drill chart look pretty, etc. plus making PDFs of each layer.
Manufacturing Output: 1% to 3% (depending on complexity and size of job. I also run the Gerbers into a 3rd party viewer just to make sure that they all line up properly).
N.B. Manufacturability (missing in poll) as a seperate activity to routing: 2% to 3% Tidying up the board by clearing acid traps, getting all the silk screen idents positioned so they don't get cliped (too much) etc. i.e. clearing all Fabrication errors in the Verify Design tool. Also things like putting little rounded courners on square pads (the nice new feature for padstacks that I am already using).
Other: At the moment that's about 10%
Anyway my ha'penny/two cents worth
Very tough question. It is different from one design to another. A design that has impedance control and matched length - FPGA and DDRs will take more time setting up constraint, board stack up and of course routing. It can also differ from design to design - how much space is available - both placement and routing will certainly depend on this critical points. I am not sure if this poll will encompass all aspects of the design steps.
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