For the last few years I've been generating schematics with FPGA's on them. In my latest design there's a 2000+ pin FPGA. I need to proof the connectivity of this part against the FPGA synthesis pinout report. I usually generate a dummy project that only contains the FPGA (and duplicate FPGA schematic) to get a netlist. Then I manipulate the netlist into an excel file. This process takes a few hours. All the data is in the schematic. Is there a way to generate a connectivity report that is easily exported to Excel? There's got to be a better way. BTW I'm using EPD 2005.