1 Reply Latest reply on Jul 22, 2013 2:55 PM by michael.weinberg

    Optimal naming of design objects


      Mentor Graphics’ Expedition Enterprise flow supports various ways of naming connectivity and PCB data such as net names and net class or constraints class names (and much more). In recent discussions with customers, we’ve found that reused naming mechanism is what enterprise customers do most often to optimize their design processes.


      One example of creating net classes in CES is to give net class a meaningful name derived from net names this class is planned to represent. Net class PWR would be set for all of the power nets (such as PWR_5V, PWR_12V etc.) to represent their common constraints such trace widths. The same in example shown below where both types of classes, diff pairs and net names match.


      classes net names example.jpg


      Mentor wants to understand customer strategies for naming convention to optimally support constraints use cases in EE flow. We would like to hear from users about it though.


      If you feel that discussion thread may be interesting or benefit to others or you have comments to it we encourage you to post your feedback.


      Many thanks!

        • 1. Re: Optimal naming of design objects

          Our application is motors and drives. Netclasses are important to us for maintaining proper clearances between netclasses. This is critical for safety and regulatory compliance.


          The company has established a list of commonly used netclasses, each designated by a 3-letter mnemonic.


          Our netnaming convention is to name each and every net, even if NC (no connection). Every net is expected to have at least one testpoint available for bare-board test.


          The netname begins with netclass mnemonic followed by schematic sheet name, signal description/function and/or increment, separated by underscores (_).


          A netname with _N or _P at the end would indicate signals of a differential pair. Active-low signals would have a dash at the end of the netname (i.e. ELV_MICRO_RD-) and active-high signals are otherwise assumed.


          We do not allow nets to be assigned to the "Default" netclass. In the PCB layout display, the nets are often colored by netclass. The "Default" netclass is the only one assigned a white color so as to stand out as an reminder that an explicit netclass assignment is pending.


          All no connect (NC) nets will have "_NC_" in the netname.


          There are many voltages and returns across many different netclasses in our designs, so a generic PWR netclass would not provide sufficient specificity.


          Some examples:




















          This convention helps in several ways:


          • Net aliases are easier to follow, locate and track throughout a hierarchical project.
          • If a net has been added and properly named but remains unassigned to a netclass (i.e. is assigned to the "Default" netclass), the question does not need to be asked of the engineer "what netclass does this net belong to?" The assignment can be made by the PCB designer and layout may progress with little interruption (however, it's good practice to always let the engineer know of any changes made to his or her schematic).
          • The matrix of Class-to-Class clearance and trace rules may be established and easily maintained for use with any new project (though these rules may evolve over time, they provide a good starting point and may allow feasibility studies to progress while final rules are being determined).
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