I want to get some layers which connect all metal layers in order to verify DRC. And I have no good idea about it.
Can anyone tell me if there are simple ways to solve my trouble.
Establishing basic connectivity through metal layers might look something like this:
CONNECT MET1 MET2 BY VIA1
CONNECT MET2 MET3 BY VIA2
CONNECT MET3 MET4 BY VIA3
Does that help, or did you want something different than typical connectivity?
Thank you for your answer. From my understanding, the "connect" keyword could not mark the net as a layer.
I want to get layers maybe like "METAL = METAL1 CONNECT METAL2 BY VIA1".
Nets and layers are different things.
A net indicates electrical connectivity, generally connecting devices. They run from the pin (or port) of one device to the pin (or port) of another, or supply power/ground like VDD and VSS.
A layer in the pure sense represents a physical plane within a chip design. (The physical layer might be broken up into different GDS layers to represent different things -- for example, metal2 might be used both within a device, and also as interconnect, and they might be represented in the GDS or OASIS database as "metal2_cap" and "metal2_wire" or similar.)
In Calibre, nets are created by the Connect statement, which tells the software "when metal N and metal M intersect, there is a connection" or "when metal N, metal M, and via X intersect, there is a connection." (Of course, statements can be far more complex than that.)
Are you perhaps thinking of derived layers, such as "gate = poly AND oxide", where poly and oxide are original layers? These are still layers, and not nets, though.
Thank you. This is what I am troubled.
From the Design Rule which my client sent to me, HV metal propagate through connecting relations and there is a rule about the space between HV metals and other metals （Of course, they are the same layer）.
So I want to have a simple way to mark nets as layers. Could you solve my problem, even if some circuitous ways.
I don't do a lot of DRC and LVS (background is in pre-xACT PEX and now RET); the quick answer would be "PERC can do that." I'm pretty sure that Chris Balcolm will be able to come up with a "pure" DRC/LVS method, though, with just a bit more information.
Is the net marked as HV with
- a marker layer (for example, in a multivoltage chip it might be part of a high power domain)
- a completely separate original layer with its own CONNECT statements
- a text label
- some other means?
By means of example, marker layers are used a lot with devices. The layers generally contain uncomplicated rectangles that are OR'd with other layers to derive devices, or zones to ignore, or regions to run different OPC products on (that's when I see them these days).
Separate original layers often show up with included IP blocks. Your original question about finding metal layers which connect to other metal layers make me think this might be the case for your design.
Text labels are probably the oldest means of naming nets, and Calibre lets you do it in a whole lot of ways: text datatypes, ATTACH statements, node inheritance... But you probably are familiar with those. Once a piece of metal involved in a net gets a text label, the label is propogated as a net name all the way along the path, ending at a port or pin. So if your nets are identified by a text label associated with the HVmetal layer, and the rule file is set up properly such that text datatype is associated with the metal datatype, then all metal layers which are part of the net will have the net name associated.
If you can answer how the metal knows it is part of an HV net, someone can tell you how to identify it for the DRC rule check.
Thank you so much!
About how to identify HV nets, it took almost all of the methods you list in my case.
Reads as follows:
Retrieving data ...