4 Replies Latest reply on Oct 23, 2012 9:04 AM by qing.fan

    spice netlist with different pins count in top level and sub cell level.

    qing.fan

      I was working on a verilog netlist with all the subcells defined in a spice netlist. LVS abort due to different pin count. The extra/missing pin vss has been defined as global in the cell.sp. LVS works fine after remove the vss pin at top level. Is there alternate solution without removing the vss pin at top level.

       

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      Here is what I have top level spice netlist (converted from Verilog) : 4 pins

       

      .GLOBAL vss

      .INCLUDE cell.sp

       

      Xroute3410 cell $PINS a=n24681 o=n29892 vcc=vcc vss=vss

       

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      Here is the cell.sp in the library spice file,  3 pins , vss is a global pin

       

      .GLOBAL vss

       

      .SUBCKT cell a o vcc

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      M1_n  o a vss vss n

      M1_p  o a vcc vcc p

      .ENDS