Are you using 2012.1 or newer? There are new bulk pin handling capabilities in the 2012.1 Tcl interface to v2lvs that may help. I haven't studied it yet myself but the section to look for is “Management of Bulk Pin Connections” in the Calibre Verification User’s Manual.
Thanks for your reply. I am using 2011.3 because of the SYNTAX error in any version later with Calibre Interactive. I am waiting for the 2012.3 coming to switch.
Right now, Calibre LVS won't run because of source netlist error. I didn't use v2lvs on the standard cells (3 pins) because those are either spice netlist or cdl netlist already. I only use v2lvs on the design level(4 pins) to convert verilog netlist to spice netlist. Unless v2lvs can remove the vss pin, otherwise, it cannot solve my problem. I will check the manul to see the options.
I have same phenomenon after upgrading.
Every parasitic instance calls master cell with extra "vss" pin.
I think you also use syntax "pex netlist ... ground vss ..."
So I used "pex netlist ... ground GND ... ".
If you do like above, you can encounter another problem that all parasitic instance definitions have GND pin as ground NOT VSS.
That's not a big problem. So I just changed GND => VSS.
If you omit "ground GND", all ground node are expressed as "0" in parasitic netlist.
If you have another good method, please leave a reply.
LVS SPICE OVERRIDE GLOBALS YES
That solved the missing pin(global pin vss) in the sub-circuit I had.