You can pour a copper shape on a layer and then 'attach' it to a pin for non-standard shapes. This will lock it into the decal, so then it can only be editted in the decal editor. You can edit the decal locally for the board, but if the decal gets updated from the library the local modifiations will be lost.
There are pros and cons for each techique (layout vs decal). I use both techniques depending upon the design. I typically will keep the ground pour at the layout level, but then you'll see many other posts from me about keeping items tied to the decal (especially regarding thermals).
The only way you can assign a net to copper in a decal is if it's associated with a pin, and therefore part of the schematic decal too. So if you put in the decal, you have to associate it with an existing pin, or add a new pin. For example, I handle all of the thermal pads for ICs with a new pin. This makes more work for the engineer when they create the schematic, and that only seems fair. The other consideration is if you need to worry about solder mask and/or solder paste, which are both handled best at the decal level.
This will be basically a GND plane under a 16 pin QFN with 13 of the 16 pins tied to it. It will be covered with mask, no soldering. I suppose I could add an extra pin and then shape it to connect to all 13 pins.
Thanks for the inputs.
As per my expereience its better to add the GND plane in Decal itself ,because most of the component having power pad required soldering to get a solid and physical connection to the GND plane .So if we are not creatinng the power PAD with enough copper pour ,there is a chance of missing the proper connection and soldering.So assign a dummy pad in decal add seperate pin for this in schematic symbol,then it will be solved all issues.
Thanks and Regards
Sabitha has a good point. When a part has a thermal pad, I define an extra pin on the part in the schematic (i.e. a SOIC-8 with 9 pins) and define the thermal pad shape. Then it is up to the circuit designer if they want to connect that copper to a net or not. This is especially important on parts when the thermal pad is tied to a net other than common/ground.
This also ensures vias don't get placed under a part with a thermal pad, unless the PCB designer takes the extra effort to remove an unconnected thermal pad first (poor practice).
Thanks for all the replies. I have added a shape and used "Associate" to tie it to a pad. However, just rec'd a "new" data sheet that shows a requirement for vias, 76 total, to be added to the GND shape. I really don't want to add 76 extra pins to the schematic symbol. How else can I add the vias to the pcb decal?
You can add all the holes that you want to a decal for an isolated thermal pad, but if you want them to connect to a net they have to show up on a schematic symbol. That is the way PADS works.
Here is how I do it:
The first entry shows the Layout view and my second entry shows the schematic view.
Via in a decal is a problem. In short, you cannot add vias to a decal, only pins. This becomes problematic at the schematic level as each pin must have a pin symbol or be listed as a "Signal Pin" which are easily overlooked.
What we have done in cases like this is this: We use the courtyard layer (20) to add design notes to PCB decals. On that layer we'd add 2D circles to represent the suggested location of thermal vias and leave some design flexibility in layout. It is in the layout that true VIAS are added to the design.
This approach allows for design flexibility in the number and size of vias used on a case-by case basis.
If the engineer has already assigned the thermal slug to a net, then the designer need only select the SMD pad, RMB and Add Via at SMD.
You will likely get many responses on this because there are several good approaches to solving this issue. All have merit. This is just what we have found works for us.
Good ideas here. I went ahead and added the vias (terminals) and used a second gate only for the vias. If my engineer doesn't like it, I will re-visit this.