I'm Lhoussain and I'm working with DDR2 wizard to simulate DDR signals.
About the used topology: I have clock routed in Y format like in the picture below
One problem that I have is the clock crossover , and after simulating with different RT values I observed that with RT values in order of 400 - 500 ohm , I have got
better results while simulations fails with the recommended values are in the order of 100ohm .
Any suggest ?