6 Replies Latest reply on Jun 20, 2013 2:02 PM by Mentor_JanetD

    Tools -> Verify Design -> Connectivity


      When I run Tools -> Verify Design -> Connectivity I get nearly 200 "Isolated Subnet" errors.  It seems to be related to any signal connected to a split plane.  The plane's properties list the appropriate signal name.  The signal name also appears in the list of signals present on that split plane's layer.  Got any ideas?  I'm using PADS 9.2.

        • 1. Re: Tools -> Verify Design -> Connectivity

          This might be stating the obvious, but the planes need to be actually poured before time of DRC under tools/poor manager.

          If they are poored at least once and you then you do a modeless command "spo" to not show poored for clarity, at that point if a DRC was done it would still show no errors.

          Only then if you clear data etc will thermal connections not show & DRC will report unconnects.


          • 2. Re: Tools -> Verify Design -> Connectivity
            David Ricketts

            A couple of other ideas.


            There's an option for Connectivity to ignore CAM plane connections. It supposed to only apply to CAM planes, not split/mixed, but be sure it's checked.


            There could be an incomplete fill, which is possible with tightly spaced designs and too wide of a pour line width. It might look good, but close-up, or in Outline mode, you might see where the pour is not filling between the vias. Change the width with the plane unpoured (SPO)  until the fill is complete.

            • 3. Re: Tools -> Verify Design -> Connectivity

              Are the errors on SMD pads?   Non-drilled pins will not show as connected if pads or thermals are defined on more than one electrical layer. Pad stacks defined with a pad on only the inner layers or on only the <Opposite side> will also be flagged as an error by default.


              Please see the Tech Note at:



              • 4. Re: Tools -> Verify Design -> Connectivity

                Performing this step got me from 200 errors down to 20.  Thanks!

                • 5. Re: Tools -> Verify Design -> Connectivity

                  Another "Bug" or "feature" --> you decide:


                  Include a net ( for example NET_EXAMPLE connecting to 3 ro more components ) on an inner layer  (for example: L2 )declared as a CAM plane.


                  Route only part of the net "NET_EXAMPLE" between terminals, using vias connecting to plane, but no traces.


                  Include only one copper pour on the inner layer (L2) say net GND.


                  Run Tools-> Verify Design -> Connectivity.


                  PADS will say "no errors" even if there are no physical traces(or copper)  connecting the different terminals of NET_EXAMPLE.



                  How I found this:

                  I came across this by acident when my PCB fab house ran a check with the netlist generated by the IPC netlister.



                  Anyone else see similar issue?


                  Is this a bug?


                  Am I using this the correct way?


                  Is the verify supposed to say "no error" assuming the user has flodded the plane with copper ?

                  • 6. Re: Tools -> Verify Design -> Connectivity

                    This issue was caused by using CAM Planes in an inappropriate manner.  Support recommended he use split/mixed planes with plane areas for layers with multiple plane nets assigned to them..