This is a very interesting and hot topic, but it isn’t the type of question that someone can answer quickly in this blog. I have seen many numbers thus far and they vary among vendors and authors. Usual range is 20MHz to 100MHz and depends on many factors as chip/package PDN, package inductance, etc.
However I would ask this question slightly differently. Assuming that you have to meet specific target impedance, what would be the highest cutoff frequency that you can achieve at board level only? You can then explore the limiting factors as capacitors’ mounting and ESL, spreading inductance of the board, stitching vias, etc. LineSim’s PDN Editor is a very good and simple to use tool that allows you do performing this type of analysis.
Another think to consider are the fundamental frequencies of the signals in your design. It is important to avoid the excitation of PDN resonances at those frequencies and their harmonics.
There are also tons of good documents that you might want to look at for better understanding. Beside Mentor’s Support website, I would suggest at least Istvan Novak’s website (http://www.electrical-integrity.com/) and Sigrity’s Technical Papers (http://www.sigrity.com/success/techpapers/support_tech_doc.htm).
A good paper that might give you useful answer is “PCB Power Delivery Optimizations for the Cost Driven Era”, by Steve Weir and Tom Dagostino from Teraspeed Consulting Group:
i will go thru all the doc. that you have recommended. Many thanks for that.
This topic is also going on in the SI-LIST group, where I have received good replies.
I found this topic very interesting and because Hyperlinks is a good tools for this kind of investigations it is important, in my opinion, to find a way that helps to determine the most appropriate Z target and F target. Not very easy I have to say.
Am doing decoupling in hyperlynx and am also having the same doubt. In some forums, it was suggested that its better to go with 100MHZ(most generic) or the operating frequency of the particular load device.
in my opinion if not different specify from the chip manufacture, 100Mhz should be fine.
Very often, due to lack of package info from the manufacture, it is impossible to do a more detail study.
You have 3 options:
1. ask to the manufacture (ie. Altera give details info about PDN Z and F Target).
2. if you have a schematic and stack-up of an evaluation board with linesim you can try to extract the PDN Z profile and use this info.
3. go up to 100Mhz
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