1 Reply Latest reply on Oct 15, 2012 8:42 AM by samantha_lizak

    LVS passed, PEX generates a wrong Calibreview


      Hi, Guys, I have a problem in PEX extraction. LVS is passed without warning or error, however, when PEX extracts RC, some warnings come out as follow:


      WARNING: pin not connected for cell ls_3P3_VDD (0) local nn = 2 net num = 1 seed_layer = 16

      pin id : 4  path: X4 name: g  type:  4   node: 0


      Then I find the Calibreview generated contains some floating nets and pins.For example, there is a label "VDD1P8" in the layout, and a pin "VDD1P8" in the circuit. In .pex.netlist, the VDD1P8 is cut into many section like "VDD1P8_30,VDD1P8_31...."(I wondering why not begins with VDD1P8_0), and connect by many p_caps and p_res. But, VDD1P8 itself is only declared once and connected by nothing. Thus in the Calibreview, VDD1P8 is a floating pin!


      Why "VDD1P8_num" doesn't begin with num=0? How can I have a right Calibreview?

        • 1. Re: LVS passed, PEX generates a wrong Calibreview

          Hi Issc-


          I'll try to help, but I have only used an old version of xRC.  What version are you using?


          Regarding the .pex netlist, that is the parasitics.  If memory serves, CalibreView is a dialect of SPICE so you should see three output files: a base name, as specified in the PEX Netlist statement; the <basename>.pex file, which has parasitics; and a .pxi file, which instantiates the parasitics.  (The .pxi may only happen for RCC and CC extraction; my memory is hazy.) The files are described in "HSPICE and Spectre Output" in the xRC manual.


          As for stuff being floating, there are many settings which could affect that.

          • Is the pin really floating?  By default, LVS does not catch that; you would need to set LVS Spice Allow Floating Pins NO.
          • Does the xcell list identify some cells with a -P flag?  That indicates that whoever set up the xcell file expects you to plug in the cell library information for those cells.
          • Are you extracting a cell by itself, without a parent?  Then the pins at the top may float.
          • Does the rule file use PEX Pin Order SOURCE?  Then if there were trivial pins that are ignored by LVS, you could wind up with floating nets in Layout.


          A good way to start debugging is to first generate a simple (non-parasitic) netlist and see if it generates any warnings.  If it does, then something in the LVS setup is not compatible with xRC. If it is clean, then you know to look at xRC settings.


          Good luck-