I am new to this forum, i found lot of wealthy discussion in this forum and like to be a part of this with my discussion too.
I am using Hyperlynx 8.1, I have created a .EBD model for the DDR3 - 1333 @ 1.5V (VLP Mini DIMM - 244 pin).
After the scuccesful creation of the .EBD model i have imported the .EBD model to the free form schematics to evaluate it.
Unfortunately i am getting an error, the screenshot of the same is attached below.
The signal i simulated was CLK_DIFF ( pin no: 186 and 187).
But surprisingly the same .EBD model works fine in Hyperlynx 7.7.
Is there any changes to do with the version of the tool or the method in .EBD creation or the Free form schematic simulation for the .EBD model....?
While simulating, we are getting the capacitors and resistors which are not physically present in the schematics as well as in .EBD file...
Could anyone please suggest solution for this................?
Thanks & Regards,