First, I suggest that you try the experiment on a signal that is not differential. The EBD syntax might not provide the means to correctly represent a DDR differential clock. If you can share the EBD file, we might be able to see if there is an error in the format, and possibly fix it.
The extra resistors and capacitors are created internally to model the sections of the EBD. If there is a Len statement with only R or only C after it, this is a discrete element. HyperLynx assigns a ref des to it to keep track of all the elements in the net.
Now, to get around the error, it might work to do this.
- Click menu Setup > Options > General.
- Click Advanced tab.
- Enable checkbox Separate pin at the same simulation node.
Hopefully, that will get rid of the error. If not, you might need to open a service request on supportnet.mentor.com.
Thanks for the reply.
We tried your solution and it worked, also we have tried with an alternate solution as:
The Clk (Clk_+ and Clk_-) signal we have directly pulled up with a 36 ohms resistor to VTT (750mV) by removing the capacitor from the path which was terminated to VDD (1.5V)
We have spliited the path description for the clk signal (pin no:186) and terminated it seperately to the VTT thorugh 36 ohms resistor.
We have divided the path description into two parts (pin no: 186 and 187)
Suggest us whether the method we tried is correct or do you have any other sugessions.
Also kindly find the EBD model with the above mentioned modification.
Also i have atached the EBD model without any modification which leads to error in hyperlynx 8.1 version.
Also i have attached the free form schematics of the EBD model of the DDR3 clk differential signal (pin no:186 and 187, without modification).
At this point i would like to ask that the EBD model without the modifications created from the Hyperlynx 7.7 works fine in that version,
Why this doesn't work in Hyperlynx 8.1.
This has anything to do with the software.... or any other limitations/enhancement..?
I might not have time to go through these files today or tomorrow. Please send me an email at firstname.lastname@example.org and I will create a regular service request for you. Or you can create the service request yourself on supportnet.mentor.com.
Both methods should work, so somebody needs to look at the files and see if there is an error in the EBD usage in HyperLynx. Did you try using either EBD in HyperLynx 8.2?
I wasn't sure what you wanted from the FFS file that you attached to your last message. It looks like you were just visually examining the connections in the EBD file. It looked OK to me, but I did not spend a lot of time looking through it.
The attached design archive has an example that I created using the two versions of your EBD. The original EBD looked wrong to me, so I fixed a couple of things around the termination. I just rearranged a few lines and removed the extra resistor after the second pin. In this example you can see the implementation of the two EBDs and compare the results using them. You can see that both work, but I don't know which one is closer to your expected results.
ebdTest.zip 576.4 KB