Would it be possible to get the data to know what exactly is causing infinite rounds of simulation ?
It turns out that this problem stems from my diode model not looking for an open switch in series with an open switch causing an unintended voltage divider to show up.
Since the SPICE diode model will cause a large schematic to be non-convergent I have had to design a diode model using SAINT.
My model looks at the voltage across the diode to determine if the ARC should be opened or closed (similar to a switch).
Since their is no way to truly open the connection in VeSys 2.0 this is a phenomena that needs to be taken into account when designing an Analysis Model.
Still why can't VeSys 2.0 detect a loop. I believe VeSys Classic had some ability to detect infinite loops and warn the user before simulating.
Also, is their a better way to create a switch? Is it really appropriate that having two switches in series will create a voltage divider (albeit no current will flow)?