6 Replies Latest reply on Oct 8, 2014 1:56 PM by yan_killy

    No Design Rule for Same Net, SMD to SMD Clearance


      Hi all, currently using PADS Layout & Logic 9.4.1 and still do not see a solution to this problem/question.  This problem/question lies on the manufacturability/ SMD Assembly side of the PCB world.  It's not a problem that will show itself in the netlist or electrical correctness of the circuit.

      I see in Design Rules, Clearance, in the Clearance Matrix there is a SMD to SMD rule the user can specify.  That rule is relevent for different net SMD to SMD clearance rules.  But what about same net SMD to SMD clearance?  Hmmmm, you ask why would anyone care about that?  Well as I hinted above this concern is not explicitly speaking a problem electrically for the circuit to function properly but a manufacturability/SMD assembly problem. If SMD pads of adjacent devices are too close together there will be either no solder mask web between them, or a mask web so thin that solder paste will wick under the mask web anyway, when the web is over Copper.  We have seen in our own in house SMD assembly process that any solder mask web less than .004"-.005" will not prevent solder paste migration, again when the web is over Copper.

      So, if you have SMD pads of adjacent devices that are that close, or even up to .010" apart (the PCB FAB house is going to grow those solder mask openings to allow for relatively poor solder mask registration leaving the PCB with maybe only a .005" web) and those SMD pads are in a Copper plane/pour they are effectively going to be one SMD pad.  Again, not a problem electrically but all kinds of bad things can happen on the SMD assembly line.  Components could start to float/drift out of position, tombstoning, a larger component could steal all of the solder from a smaller one, take your pick of problems.  Of course AOI will catch these problems but if you are waiting for AOI to catch your problems you've already committed the mistake to a fabricated PCB and signed up for expensive hand solder rework AND another spin of your PCB.  Better to catch it up front right?


      A new rule in the Design Rules, Clearance, Same Net Matrix for SMD to SMD would catch this type of problem right?


      Is there some specific reason Mentor has seen fit to not include this Design Rule?


      Is there some aspect to Decal design that I am not familiar with that can effectively prevent this, and/or allow existing design rules to flag this type of problem?


      The attached picture shows just such a problem between L4 and (C81 & C82).

        • 1. Re: No Design Rule for Same Net, SMD to SMD Clearance



          Consider using Fabrication check in Verify Design. Setup for Fabrication checks two parameters 'Pad To Mask' and Solder Bridges Minimum Gap. Let me know if this will work for you.

          If this is not what you need, consider adding DFMA (Design for Manufacturing Analysis) module.


          Regards, Yan

          • 2. Re: No Design Rule for Same Net, SMD to SMD Clearance

            Thanks for the information on the Verify Design, Fabrication Set Up.  I had not considered this area.  Though based on the definitions described in Help it does not look like either the Pad to Mask or Solder Bridges checks will do what I am looking for.

            Additionally I was looking for a Design Rule so that it could be something that can be set and synched in from the schematic.


            I will look at the DFMA module as well though.  Yan, can you give me a pointer to the DFMA module you are referring to.  I am only finding eSIGHT DFM.



            • 3. Re: No Design Rule for Same Net, SMD to SMD Clearance

              I got a similar problem and could not work it out by setting different rules.


              I want to separate some power ground traces from the ground plane when doing pouring. In the design rule, I selected "net" and chose the "gnd" net and set the same net clearance of "trace" to 0.2mm. But when doing pouring, the ground traces are still covered by the ground plane.


              In Allegro or Altium, it is much easier to set the same net clearance of "trace" to "plane". Any idea how to do it in PADS Layout?

              • 4. Re: No Design Rule for Same Net, SMD to SMD Clearance

                Peng-he I have seen this same issue when routing sense lines through a split mixed plane. The only method I have found to get around this has been to use a keepout to keep the plane from flooding over the trace. Also make sure to protect these routes if your doing this under a location where there are multiple pins of that same net.

                • 5. Re: No Design Rule for Same Net, SMD to SMD Clearance

                  I have a jumper component (JU1, JU2, etc.) defined (Mentor has a jumper that is similar) that I use to connect my sense lines to my power net.  This way it looks like separate nets to Layout and is much easier to maintain.  The caveat is that I always have a clearance violation at my jumper component. it is easy to ignore the violation at a "JU" component.  I keep a clearance report showing that the only accepted clearance violations were at the jumper components. 

                  • 6. Re: No Design Rule for Same Net, SMD to SMD Clearance



                    Consider using Copper with Bridge option that allow to short two or more different Nets without creating a spacing errors yet maintaining electrically the nets separated. It just like a Mecca point got different grounds (GND, DGND, AGND, etc.)


                    Regards, Yan