1 Reply Latest reply on Jan 11, 2013 7:16 AM by michal_ferdek

    problem with the build in Altera Pinning Rules and DDR-II Interface

    o.mahren

      Hello,

       

      I have a problem with the IO-Mapping of a existing FPGA Design (Altera / Cycole IV E 40K).

      The IO-Designer don't Map some Pins because he mean that this Pin mapping is against some Altera Mapping Rule (-> This rule can and on may design must be override with a Altera assignment).

      If I import the Pinning I become this Error Messages .....

       

      cannot assign signal 'lvds_tx<3>' to 'AD26,AC25' - Swap groups of signal lvds_tx<3> and pins AD26,AC25 are not compatible

      cannot assign signal 'mem_a.addr<12>' to 'F14' - Output pad with IO standard SSTL-18 CLASS I has to be at least 2 pads away from VREF

      cannot assign signal 'mem_a.addr<6>' to 'G16' - Output pad with IO standard SSTL-18 CLASS I has to be at least 2 pads away from VREF

      cannot assign signal 'mem_a.addr<7>' to 'D16' - Output pad with IO standard SSTL-18 CLASS I has to be at least 2 pads away from VREF

      cannot assign signal 'mem_a.cas_n' to 'D11' - Output pad with IO standard SSTL-18 CLASS I has to be at least 2 pads away from VREF

      cannot assign signal 'mem_a.ras_n' to 'K13' - Output pad with IO standard SSTL-18 CLASS I has to be at least 2 pads away from VREF

      cannot assign signal 'mem_b.addr<5>' to 'AE15' - Output pad with IO standard SSTL-18 CLASS I has to be at least 2 pads away from VREF

      cannot assign signal 'mem_b.addr<7>' to 'AA16' - Output pad with IO standard SSTL-18 CLASS I has to be at least 2 pads away from VREF

      cannot assign signal 'mem_b.addr<8>' to 'AC17' - Output pad with IO standard SSTL-18 CLASS I has to be at least 2 pads away from VREF

      cannot assign signal 'mem_b.ba<1>' to 'AF18' - Output pad with IO standard SSTL-18 CLASS I has to be at least 2 pads away from VREF

      cannot assign signal 'mem_b.cas_n' to 'Y15' - Output pad with IO standard SSTL-18 CLASS I has to be at least 2 pads away from VREF

       

      It is true tat such a Altera Rule exist, but for the 2 DDR-II Interfaces is defined (Altera Assignment)  a Output Group so that this Rule will be ignored bay the Altera Compiler (Altera automatic Pin Mapping).

      This is Correct for may design and the design will be OK (from Altera Side).

      I can't change the mapping so that the ALTERA rule in the IO-Designer will be accept the (correct) pinning ! (-> to less Pins)

       

      The question is ...

      Can I override the Pin Mapping in IO-Desiger so that he accept this Pin mapping ?

      Or is there any way to deactivate this build in IO-Designer Rule ?

      Or is there any way tat the Mentor IO-Designer accept also like the Altera Quartus Tool the grouping assignment so that both accept this exception from the standard rule ?


      For Better understand -> The Altera Pinning is correct, I can't change the FPGA design so that the IO-Designer will accept the Pinning with the build in Mentor rules !!!