3 Replies Latest reply on Jan 18, 2013 3:53 AM by yu.yanfeng

    Not translating pads on vias and pins correctly from Allegro to boardsim

    SiliconPhotonics

      Hi,

      When I use the via properties or visualizer in Hyperlynx boardsim, it still shows the pads on the layers unused/unconnected with the via or pin. I did remove those pads on unused layers in Allegro and I can see those pads are gone in Allegro.

      Does anyone has this problem?

       

      Thanks,

      Han