SiliconPhotonics

Not translating pads on vias and pins correctly from Allegro to boardsim

Discussion created by SiliconPhotonics on Jan 16, 2013
Latest reply on Jan 18, 2013 by yu.yanfeng

Hi,

When I use the via properties or visualizer in Hyperlynx boardsim, it still shows the pads on the layers unused/unconnected with the via or pin. I did remove those pads on unused layers in Allegro and I can see those pads are gone in Allegro.

Does anyone has this problem?

 

Thanks,

Han

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