I am trying to simulate by DDR wizard of hyperlynx 8.2.1 the SDRC port of Sitara AM3730 connected to a LPDDR MT46H64M16. The issue is that I am using the timming model included in hyperlynx instalation (lpddr_ctrl.v). Could you let me know if this model is valid for my controller?. For DRAM I am also using lpddr_dram.v included in hyperlyns. I am getting setup and hold errors on data bus. It is a little strange so I think the timming model I am using is not valid.