6 Replies Latest reply on Feb 4, 2013 12:13 PM by dan_liddell

    Trouble in calibre LVS understandin

    lakshmiprashanth555

          Hi,

       

           Myself Lakshmi Prashanth.A.N, I'm a layout out designeer at Analog devices india pvt ltd. I'm new to calibre LVS and i've lot's troubles in it. But currently I want know what is $PIN & -i in calibre LVS, what is the use of it, what is so special about, why it is coming in every v2lvs execution. And how to merge netlist in calibre, to single netlist.

        • 1. Re: Trouble in calibre LVS understandin
          jean.david

          Hi

           

          For $PIN have a look to documentatiion

          "Calibre Verifiaction User's Manual --> V2LVS --> Library Interface Files --> V2LVS Used With SPICE Library Files

          --> Use of Range Mode

          --> Use of Pin Mode

           

          v2lvs command arguments :

          • -i

          Specifies that calls to subcircuits with pins be  done in order, according to traditional SPICE rather than with $PINS  construct. Calibre nmLVS has a special SPICE extension for named pin  connections in the $PINS construct. This option is for non-Calibre  applications only. See "Generate Simulation Output" for details.

           

           

          If you want to merge netlists in single one use option -s

          -s spice_library_file_one

          -s spice_library_file_two

          -s ....

          Specifies that the -o option output file has a .INCLUDE statement that points to the SPICE library file. The -s option does not cause V2LVS to read the library file. This option may be specified multiple times. See the -lsp and -lsr options for reading SPICE library files.

           

          regards

           

          Jean

          • 2. Re: Trouble in calibre LVS understandin
            lakshmiprashanth555

            Hi,

             

            Thanks for the previous answer. And I've another doubt, Is their any way to use verilog in calibre instead of spice directly, if their is a way please guide me.

             

            Thanks and Regards,

             

            Lakshmi Prashanth.A.N

            • 3. Re: Trouble in calibre LVS understandin
              jean.david

              Hi

               

              Input source netlist format available :

               

              SOURCE SYSTEM {CNET | SPICE}

              Used only in Calibre nmLVS/Calibre nmLVS-H and Calibre xRC.

              Parameters

                  CNET

              Keyword that specifies that the source is a compiled netlist (Cnet) database.

                  SPICE

              Keyword that specifies that the source is a SPICE, SPICE 2, HSPICE, or CDL netlist, or a Verilog netlist converted into extended SPICE form.

               

              regards

               

              JEan

              • 4. Re: Trouble in calibre LVS understandin
                lakshmiprashanth555

                Hi JEan,

                 

                Thanks for help, but it help me only a little, My exact problem is that as follows,

                 

                for example:   we have a toplevel verilog file, with connectivy as follows, assume STH_INV has ports for VDD, VSS, IN , OUT, when converting it to spice file using v2lvs using command "v2lvs -s0 VSS -s1 VDD -v file.v -o snapper.spi" it is providing a miss-match with the port, where verilog ports are different from spice file port,

                                      So we decided to merge all the cir, and wir files the verilog in the v2lvs command, like " v2lvs -s0 VSS -s1 VDD -v file.v -lsp file_1.cir file_2.cir filer_3.wir -o output" we tried using -lsr also, we are trying different solutions, but we are failing, please give us a solution.

                 

                                     we have another problem converting verilog to spice like this by -i switch:

                Error: No module declaration for module STL_CKGTPLT_V5L50_4 first encountered in module SNPS_CLOCK_GATE_HIGH_sms_proc_top_ieee1500_0_0.

                       (-i switch requires Verilog declarations for all modules.)

                Info: Exiting v2lvs.

                 

                                     if we exectute the v2lvs without using -i, we are getting only warning as no module declarations like this, when we use the -s for every cir file,

                Warning: No module declaration for module STN_ND3_S_2 first encountered in module snapper

                Warning: No module declaration for module STH_BUF_1P5 first encountered in module snapper

                Warning: No module declaration for module STN_BUF_CTEY2_48 first encountered in module snapper

                Warning: No module declaration for module STN_INV_SL50_5 first encountered in module snapper

                etc......

                 

                 

                                     But we have give module declaration for that  and we have cross verified it.

                • 5. Re: Trouble in calibre LVS understandin
                  jean.david

                  Hi

                   

                  First we generate verilog netlist from IC Compiler (Synopsys) or EDI (Cadence) with these following commands:

                   

                  ICC: write_verilog -diode_ports -split_bus -pg -output_net_name_for_tie layout_ntl_pg.v

                  EDI: saveNetlist -includePowerGround -includePhysicalInst -phys  -excludeLeafCell layout_ntl_pg.v

                   

                  We have all spice netlist for standard cells ,IP blocks, buffers.

                  my_all_spice_netlist.cdl contains for example

                  .include inverter.cdl

                  .include rom.cdl

                  .include buffer.cdl

                  ..

                  ...

                   

                   

                  v2lvs -s my_all_spice_netlist.cdl \

                           -v layout_ntl_pg.v \

                            -lsr my_all_spice_netlist.cdl \

                            -n \

                             -a "<>" \

                             -u UNCONN_ \

                             -s1 G_P -sl -sn \

                             -o my_chip.cir

                   

                  regards

                   

                  Jean

                  • 6. Re: Trouble in calibre LVS understandin
                    dan_liddell

                    Assuming a 2012.4 build, the Calibre Verification User's Manual describes all of the command line options in a section entitled "V2LVS Command Line Syntax." Each option is briefly described. Links are provided to detailed discussions of options. Sometimes it's necessary to read the details to understand completely what an option is going to do.

                     

                    If you are having difficulty with supply ports being matched, the section "Power and Ground Connections" is important to understand. There is a table in that section called "Mapping of 1'b1 Signals" that discusses the use of all the supply (-s*) options. It is important to look at the Verilog code and the SPICE output to understand how these options translate things. You may have to start with a smaller module and concentrate on getting that right before moving on to bigger blocks.

                     

                    The section "V2LVS Used With SPICE Library Files" discusses how to choose SPICE library options. The use of -lsr and -lsp is discussed in that section in detail. If your Verilog file treats something like A[0:3] as a port range, then use -lsr. If a module treats A[0:3] as individual pins, then -lsp is needed. It is possible you may need to mix and match the -lsp and -lsr options if your Verilog modules use both range and pin modes.      

                     

                    If you have primitive Verilog library files, you need the -l (small L) option to specify each one. If you have SPICE library files, you need the -s option to get all the .INCLUDE statements into the SPICE output. You can also put the .INCLUDE statements into the output manually, but the tool will do it for you with -s.

                     

                    If you can't get things to work after reading and experimenting, I suggest opening a service request at https://supportnet.mentor.com.

                     

                    dan