LVS question how to flag floating "island" of MOS devices in the layout

Discussion created by hstoiber on Feb 9, 2013
Latest reply on Feb 14, 2013 by hstoiber

Hello.  Have anyone encountered a situation where the schematic has an unintented error where the source of PMOS devices was tied to a non-port supply power net name and the source of the NMOS devices was tied to a non-port supply ground net name, and thus, the layout followed the schematic and passed LVS, however, since the supply power and ground nets in the layout though were hooked up to the MOS devices, were actually floating inside the layout and not hooked up to the supply power and ground pins and thus eventually not hooked up to any IO pads in the layout which eventually resulted a non working chip since these devices were actually not driven by any supply nets?


Beside, PERC and ERC, is there anyway to make this LVS not clean?  Is there anyway to make LVS failed if the MOS devices are not driven by supply net names?




-Hazel Stoiber