3 Replies Latest reply on Feb 19, 2013 9:02 AM by mark.lin

    negative width in LVS

    mark.lin

      I had a very awkward shape of MOS cap which is LVS-clean except for its negative calculated LVS width.    Is there any command that I can mask the size checking of this MOS cap in Calibre?

        • 1. Re: negative width in LVS
          chris_balcom

          There should be a TRACE PROPERTY statement if the size is being checked. Commenting or removing that statement should prevent checking of the related property for all devices of the type specified in that TRACE PROPERTY statement.

          • 2. Re: negative width in LVS
            mark.lin

            Thank you, Chris.   My problem is that "The PMOS cap is the generic type, e.g., MP(pfet).   Therefore, I cannot manipulate TRACE PROPERTY unless I create a brand new pfet type to specifically refer to the pfet used only for the capacitor purpose"     Since it is inside the pixel and if I cannot eliminate this irrelevant property error, the whopping amount of property errors from this negative width in the final chip may obscure the other true errors.

            • 3. Re: negative width in LVS
              mark.lin

              Unless anyone has a much better way to solve this negative width problem, I ticked this off as solved.   I just used a precarious way to temporarily eliminate the LVS error, i.e., in the LVS rule file, I add "if (width <0) width=3.999" in the property definition section.