4 Replies Latest reply on Feb 26, 2013 5:41 PM by thana_raj88

    croswell violations in IC design

    thana_raj88

      As the title above, what is crosswell violation in a ic design. Kindly need some references or notes regarding it, thanks.

        • 1. Re: croswell violations in IC design
          samantha_lizak

          Hi Thana-

           

          To the best of my knowledge, this is not a predefined Calibre check -- you'll need to ask the group who provided your rules what they mean by it.  A quick Google search showed there are a number of things which you do not want to have cross well boundaries; the term could refer to any of them.

           

          If this is a tool other than Calibre, would you please provide more details?

           

          Regards-

           

          Sam.

          • 2. Re: croswell violations in IC design
            thana_raj88

            Hi Samantha,

             

            Thank you for the reply. Actually i'm refering it to IC Compiler (SOC_design). A power well triangle is applied in every chip design which is the boundaries for different type of cell. For example, cell that will turn off first when you shut down your system or cell that will be always in on state. Isolation of a signal is needed if the signal was driven from a partition with a different power plane to the load of the signal. So i'm actually looking for a proper documentation on this cross well violation and some solutions if you encounter one.

             

            Thanks.

            • 3. Re: croswell violations in IC design
              samantha_lizak

              Hi Thana-

               

              IC Compiler is a Synopsys product.  It is true that Calibre Interactive can be integrated with it, but if the error is coming from IC Compiler it could be one of its checks.  If this is showing up as a (Calibre) DRC or PERC error, look in the SVRF rule file for the exact check.  I can help you interpret SVRF rule checks if you post the appropriate lines, but really the best people to help with it are the ones providing the rules -- usually a foundry or sometimes your company's CAD group.  I can tell you what the code says, but they could tell you why it is there and maybe some potential fixes.

               

              If you are working at a university or otherwise can't get direct support for the PDK you are using, a good forum is EDA Board - http://www.edaboard.com/forum.php .  I've seen engineers post questions about errors they are getting; usually the first thing people ask is which foundry/process and what software & version.

               

              Sorry I can't help more -- the only thing I know about IC Compiler is what we list in the Calibre Interactive manual for tool integration.

               

              -Sam.

              • 4. Re: croswell violations in IC design
                thana_raj88

                Hi Samantha,

                 

                Thank you for the concern. I will try to do things like you said and maybe if i can get a solution i will post it here.

                 

                Regards,

                Thana