Getting errors while doing DDRx batch simulation read cycles

Discussion created by sk00101683 on Mar 5, 2013
Latest reply on Mar 25, 2014 by elena.dragomir



I am doing the DDRx batch simulations for DDR3 interface (DDR3 routing is completed and other interfaces routing is partially done)


I am not getting any issues while doing the data timing on write cycles, address/command/control timing simulations and clock to strobe timing simulations. I am getting error only in the read cycles and the error message is "missing driver models: unable to simulate"


I have assigned IBIS models and mapped pin assignments automatically from the tool. And also i tried manual pin assignments for DDR data bits and address bits. No use.


Can somebody Help me to to solve the this issue?