Via modeling - 3D

Discussion created by kbmani on Mar 15, 2013
Latest reply on Mar 19, 2013 by kbmani



In hyperlynx 8.2.1, via modeling is possbile using 3D EM solver. It is allowed if the via is connected between two layers.


If I have a via with three ports ( one to the top, 2nd one to an inner layer and 3rd one to bottom), 3D EM is not possible.


Does it mean 3D is not possible if I use a standard via ?


Please explain the reason behind this.