This is what I get from Calibre LVS report. Seems like it complained something about the m factor but I could be wrong. Could somebody lighten me up on this subject?
I also attached the schematic (see below, the transistors that calibre are complaining are MM0/MM3 and MM1/MM2 which are connected to the same input Gates but layout have the Source/Drain sharing in Series Folded Cascade. One more note, If I turn on Share Equipotential under LVS Options under the Gate Tab, these Property Error are cleaned!! I'd like to have a better understanding of what's going on.