1 2 First Previous 19 Replies Latest reply on May 27, 2013 5:24 PM by dan_liddell

    Can identify the every MOS on layout with calibre tools/command?

    tungyi.cop00g

      Hi,everyone.

       

      As title.

       

      If it can identify the MOS, is it possible to find the voltage on

       

      the metal line which connected to the G/S/D by connecting

       

      the netlist simulation to gds layout?

       

      Thanks.

        • 1. Re: Can identify the every MOS on layout with calibre tools/command?
          dan_liddell

          Hi Tungyi,

           

          I'm not sure I understand exactly how you plan to get the simulation voltage values. Calibre doesn't do voltage simulation (like solving loop and node equations). You would have to get that information from a voltage simulator.

           

          You can identify MOS devices in the layout in two ways.

           

          First is the DEVICE statement. When you run netlist extraction, the MOS devices will appear in the layout SPICE netlist. The $X and $Y properties indicate the coordinates of the lower-left corner of the device body.

           

          Second is the DEVICE LAYER statement. It can be used in an ERC check to locate device body shapes. You can use the ANNOTATE keyword along with LVS ANNOTATE DEVICES to attach special properties to the devices in memory. If you already have simulation voltage values and you want to annotate devices with those values as properties in the extracted netlist, then this is functionality you may want to try.

           

          dan

          • 2. Re: Can identify the every MOS on layout with calibre tools/command?
            tungyi.cop00g

            thanks lot.

             

            But the syntax DEVICE which is only "the device" information is not output the connected line information.

             

            Even though knowing the node voltage, we still can't identify the specific MOS and the specific metal line

             

            connected to the MOS gate and print the voltage on Virtroso windows.

            • 3. Re: Can identify the every MOS on layout with calibre tools/command?
              dan_liddell

              Hi Tungyi,

               

              Unfortunately, I don’t know the details of your flow. Some questions:

               

              Do you already have the loop and node equations solved by some tool? If not, how do you plan to get that data?

               

               

              Do you want the voltages to appear as properties in an extracted SPICE netlist? If not, where do you want them to appear?

               

               

              Do you want the voltages to exist as properties in your layout?

               

              Thanks,

              dan

              • 4. Re: Can identify the every MOS on layout with calibre tools/command?
                tungyi.cop00g

                Hi, Dan,

                 

                Many thanks for your reply.  I'm Tung Yi's thesis advisor.  I asked him to search for the answer to the problems he ran into in his thesis project.  I guess we are lucky to receive your reply and you seem to be quite knowledgeable on the usage of EDA tool.  We are new on Calibre. However, we must use it to accomplish the project work here.  First, let me summarize what we would like to know as follows:

                 

                What we want to do:

                 

                We have physical layout (including front-end transistors and back-end metal lines) of a circuit.  However, we do not have the schematic of the circuit and we do not have its netlist file either.  The quetions are

                 

                - Can we extract Spice netlist file from the gds file of the physical layout we have?  If yes, then how?  Can you advise us what commands to use from Calibre and how to use them to do this job, and also specifically from which part of the Calibre user manual we are able to see and understand these comamnds.

                 

                - Once the spice netlist file becomes available, we wouild like to run circuit simulations using a ckt simulator such as Cadence Spectre to solve voltages in every node of the transistors in the circuit.  Once the node voltages of every transistors are avavilable, we woul like to find out where these node voltages go to the interconnect metal lines above these transistors.  This will need to require the knowledge of the connectivity information between the transistor nodes and the interconnect metal lines above.  How do we find out the link to the connectivity in between the transistor nodes and the metal lines?   Our goal is to eanble post-processing the voltage information for interconnect metal lines.  Can we achieve this?  Can we also label the voltage values on the metal lines in the physical layouts? 

                 

                We really hope you or someone in this forum can answer our questions here.  We have not been able to move froward in our project work for some time already due to the above problems which we do not have knowledge to solve. 

                 

                We wish the above provides a clear picture for the problems we encountered here and we sincerely look forward to your reply.  Hopefully the reply will get our project going again.

                 

                Best Regards,

                 

                Tom

                 

                 

                 

                 

                 

                   

                • 5. Re: Can identify the every MOS on layout with calibre tools/command?
                  dan_liddell

                  Hi Tom,

                   

                  I’m happy to help. Let me begin by asking if you have a SupportNet account. If the answer is no, could you please ask your Mentor Graphics contact about setting you up with an account? Once you have one, I suggest going to this page:

                   

                  http://supportnet.mentor.com/downloads/related/calibre_utilities/files.cfm

                   

                  Click the “Calibre Example Kits (eKits) and Tutorials” link at the end of the first set of bullet items. Scroll down through the Example Kit table and select this file:

                   

                  calbr_QS_ekit_2012.3.tgz

                   

                  Unpack the file and work through the LVS and PERC modules. These tools will be of interest to you.

                   

                   

                  I’ll quote your questions and respond.

                   

                  Q: Can we extract Spice netlist file from the gds file of the physical layout we have?  If yes, then how?

                   

                  A: You will need a connectivity extraction rule file. Once you have this rule file, you can execute ‘calibre –spice layout.sp rules’ and the layout.sp file will have your extracted netlist.

                   

                  Q: Can you advise us what commands to use from Calibre and how to use them to do this job, and also specifically from which part of the Calibre user manual we are able to see and understand these commands.

                   

                  A: A good place to start for some fundamental ideas is the quick start package I refer to previously in this mail. Another good place to look is the Calibre Solutions for Physical Verification (calbr_solns_pv_user.pdf). In that book, the “LVS Best Practices” chapter would be good to read. The “Basic LVS Rule File Template” section will also be useful if you don’t already have a rule file. You won’t need to worry about LVS comparison because you don’t have the source for the design, but all the portions that relate to circuit extraction will be relevant.

                   

                  For all rule file commands, you will want to consult the SVRF Manual (svrf_ur.pdf). Many of the commands are directly linked to from other books. One section in particular that is worth looking over is the “Key Concepts” chapter, particularly the “Basic Rule File Structure” and “Rule File Elements” sections. Not everything will be relevant to what you want to do.

                   

                  Another manual you should become familiar with is the Calibre Verification User’s Manual (calbr_ver_user.pdf). In particular, you will want to review these sections:

                   

                  Invocation > DRC and LVS Command Line Syntax > Calibre nmLVS and Calibre nmLVS-H

                   

                  Layout Processing Concepts (You can safely skip parts that are DRC-centric, like rule checks, unless you want to perform such things as a part of ERC.)

                   

                  Connectivity Extraction (Skip the parts about incremental connectivity and connectivity in DRC.)

                   

                  Device Recognition (Skip everything including device signatures and later for now, except for Bad Device Reporting. You can come back to that material if needed.)

                   

                  Q: How do we find out the link to the connectivity in between the transistor nodes and the metal lines?

                   

                  A: Since the metal lines are part of a physical layout and your simulation data is presumably topological, this is a difficult problem because topology has no mapping to a coordinate system or to layers. If your simulation data has physical location information in it, that would make things easier, but I’m guessing this is not the case.

                   

                  Q: Our goal is to eanble post-processing the voltage information for interconnect metal lines.  Can we achieve this?  Can we also label the voltage values on the metal lines in the physical layouts?

                   

                  A: You can assign properties to layout objects in memory and process those properties using user-defined programs, or even export them in annotated GDS as property records. But getting properties from a topological simulation world to a geometric layout world is the problem. I don’t know of a solution to that.

                   

                  This raises another question. What are you planning to use this voltage information for?

                   

                   

                  dan

                  • 6. Re: Can identify the every MOS on layout with calibre tools/command?
                    dan_liddell

                    Hi Tom,

                     

                    After doing some asking around, I have a solution for you. It will require use of the Calibre PERC LDL framework. The manual for this is not included in the standard Calibre documentation. You can ask your Mentor Graphics representative to obtain a copy for you.

                     

                    The Calibre PERC User's Manual and the Calibre PERC module in the Quickstart package I mentioned before will also assist you in getting started. In the user's manual, you'll want to pay particular attention to the first 7 chapters, except for the one about pattern matching.

                     

                    Proficiency in coding Tcl is needed to use the tool successfully.

                     

                    Your flow will be as follows:

                     

                    1. Create your netlist extraction rule file. The documentation references I gave you in my previous post should assist you in doing this.

                    2. Extract your layout netlist as I discussed in my previous post.

                    3. Generate your nodal voltages using the simulator.

                    4. Write a PERC topology rule file to operate on your extracted layout netlist. In that rule file, you will need to define voltages for all the nets that have them. This is done using perc::define_net_voltage_by_placement (it can also be done using perc::define_net_voltage, but that may not suffice for your situation). You will then want to export all the nets with voltages. This is done using perc::export_net.

                    5.Write a PERC LDL rule file to import your nets and tag them with the voltages. You will want to use the source-based flow, which uses the ldl::export_perc -source option (your source in this case will be your extracted layout netlist, since that's what you'll have). This is discussed in the PERC LDL DRC manual. You will want to use the -forward_hcell option also. If you have no hcell list (discussed in the Calibre Verification User's Manual), just use the top-level cell. To bring in the nets, use the ldl::select_nets command with the -props option. This will attach voltage properties to the polygons.

                     

                    Hope this helps,

                     

                    dan

                    • 7. Re: Can identify the every MOS on layout with calibre tools/command?
                      tungyi.cop00g

                      Hi, Dan,

                       

                      I'm TungYi, thank you very much for your reply and help. My advisor is not here until tommorrow.

                       

                      So, I didn't reply your emails immediately. I already have requested the manuals which you mentioned before.

                       

                      Also, I produced netlist file for one small block of the layout. I am waiting for my advisor to reply you more information now.

                       

                      TungYi

                       

                       

                       

                       

                       

                       


                       

                       

                       

                       


                      • 8. Re: Can identify the every MOS on layout with calibre tools/command?
                        dan_liddell

                        Hi TungYi,

                         

                        Most of the documentation is available in the Calibre binary package starting in 2013.1. (The PERC LDL DRC manual is not, as I mentioned earlier.) Prior to that, the documentation was in a separate bundle. You can access the downloads from SupportNet here:

                         

                        https://supportnet.mentor.com/downloads/index.cfm?id=201303069&product=C110-S105-G217-P10099&redirected=true&reason=0

                         

                        If you don’t have a SupportNet account yet, you might want to consider requesting one.

                         

                        One thing you will need to do is to create a script that parses your simulation data for net names and voltages. In the Calibre PERC User’s Manual, there is a section called “Useful Utility Procedures.” Under that section, there is an example script called define_net_voltages_from_file. This is a Tcl procedure. It makes some assumptions about what the data looks like in a file that it reads. Those assumptions are these:

                         

                        1. Lines in filename are expected to be of these forms:

                        2. <net_name> <voltage_value> [<voltage_value> ...]

                         

                        If your simulator data doesn’t look like this, you’ll need to do some modification of the script. This requires some knowledge of Tcl.

                         

                        The script as it stands is designed to run within Calibre PERC. But you can get it to run in a Tcl shell (tclsh) outside of PERC by making some modifications to this section:

                         

                           

                        1. For each voltage-net list, generate a perc::define_net_voltage command

                            foreach $voltage_type_list {       perc::define_net_voltage "$" \

                               

                         

                        As this is written, the information would be available only in the PERC system. If you want to make it available in the Tcl shell, you can do something like this:

                         

                        set outfile

                        foreach $voltage_type_list {   puts $outfile "perc::define_net_voltage \"$\" \n”

                        }

                        close $outfile

                         

                        Your perc::define_net_voltage statements will be in net_voltages.txt. (I haven’t actually tested this, so be aware I may have made a syntax mistake. But, this should give the general idea.)

                         

                        You’ll also need a call to the main proc in the script to get everything to run, so you’ll need something like this:

                         

                        define_net_voltages_from_file simulator_output_file.txt

                         

                        Once you have a script like this that works, you’ll be ready to incorporate it into your PERC flow to get your net voltages into the system.

                         

                        dan

                        • 9. Re: Can identify the every MOS on layout with calibre tools/command?
                          tungyi.cop00g

                          Hi, Dan,

                           

                          Many thanks for your three replies which were very informative and useful.  We are still in the process of digesting your message now.  Here we would like to give you an update on what we have done and are doing now as follows:

                           

                          - Tung Yi has been following up your suggestions in these couple days.  He has been able to obtain some of the manuals so far.

                           

                          - Since we are in a university system where all the EDA tools we are using were not purchased by us (our Lab), we were told that we will not be able to obtain the SupportNet account from Mentor Graphics.  However, we were able to get the document of calbr_QS_ekit_2012.3.tgz you suggested from another source.  Nonetheless we may have problems in getting other documents you suggested in your replies if we cannot locate them from other sources.  We will give you an update next week on how many manuls and the list of their names we secured by then.

                           

                          - Tung Yi was able to generate a netlist file using the layout GDS file and the rule files (from TSMC) for a small block (approximately with 70K Transistor count) of circuit.  By the way, we forgot to mention you previously that the circuit we used is a digital circuit with transistor count around 800K.  We are afraid that you may have mistaken that our circuit to be an analog circuit which usually requires more detailed transistor-level simulation analysis.  Our concern here is for all your teaching to us here on how to solve the problems and do our jobs here, is it for analog circuit which usually is quite small.  Or is it general for all type of circuits, large and small?  Can what we are learning here do the job and achieve the goal of our project task on a large digital circuit without any problems or issues? 

                           

                          - For your question on how we plan to use the extracted voltage information, here is the answer:  The voltage information obtained from Spice simulation will be applied to the interconnect metal lines.  This is the reason why we need to find the connectivity information between the metal lines and the transistor nodes.  We will process these voltage information for interconnect study.  One question here is when you mention topology simulation, what does it mean?  Our simulation will be Spice circuit simulation, does it belong to the category of topology simulation? Another question is we would like to attach the voltage information to the metal lines, so in your writing of “will attach voltage properties to the polygons”, is the polygons here the metal lines?

                           

                          We will do our best here to follow up your guidance here.  We will give you update frequently for both our progress and the problems or new issues surfacing up.

                           

                          We very much appreciate your dedicated and selfless service in the EDA tool community.  We are really lucky to encounter you.  We highly regard your professional expertise and sincerely hope that you will be able to guide us through so that our project here can be successfully completed.

                           

                          We will update you again soon.

                           

                          Best Regards,

                           

                          Tom  

                          • 10. Re: Can identify the every MOS on layout with calibre tools/command?
                            dan_liddell

                            Hi Tom,

                             

                            You’ll have a lot to digest between the references I cited and the Quick Start package. All of that will help you get oriented with the tools. I suggest trying out examples in the documentation as you read them by adapting them to either your layouts, or to the data you find in the Quick Start tarball.

                             

                            Regarding analog versus digital designs, yes, analog simulation is more typical. I’ve not tried what you are planning to do on a larger digital block. However, I think Calibre PERC will be able to do what you seek. Hardware (memory, specifically) might be a constraint, depending on the machines you have available to you. I suggest starting out with a smaller block and getting that to work before tackling bigger things.

                             

                            Yes, topological simulation includes SPICE simulation. This is in contrast to layout simulation tools that compute things for polygons like resistance, current density, and so forth, for objects in the physical layout.

                             

                            As far as attachment of properties (like voltages) to polygons go, those polygons can be from any layer in your design. So if you want the properties on metal, that’s where you’ll have them. If you want them on polysilicon, diffusion, wells, and so forth, that’s all doable.

                             

                            I noticed in my previous post to Tung Yi that this link text comes through in numerous unexpected locations: “Re: Can identify the every MOS on layout with calibre tools/command?” I didn’t write that. What I had was variable names starting with the dollar character. You’ll see them in the documentation when you look at the utility proc I cited. Somehow the communities bulletin board turned those variables into the string that is the name of this thread, which is a little confusing.

                             

                            In an earlier post, I gave you the general PERC LDL flow you will use (5 steps). In step 4, I forgot to mention one command. perc::check_net will be needed to identify all nets in the design. You will use that command with the –condition option to call another Tcl proc. That Tcl proc will use perc::export_net to export the nets to the LDL module, which is where the properties will be attached to polygons. This is probably all Greek now, but I hope it will get clearer once you have a look at the manuals and Quick Start data.

                             

                            What I’ve given you up to this point should be enough to get you up and running. I won’t promise any level of support in the future, but I can try to answer specific questions that come up.

                             

                            Have fun.

                             

                            dan

                            • 11. Re: Can identify the every MOS on layout with calibre tools/command?
                              tungyi.cop00g

                              Hi, Dan,

                               

                               

                              Thanks for your reply and suggestion.  We are still in the process of digesting the inputs from you.  As far as the manuals are concerned, the following lists what we have located so far:

                               

                              calbr_QS_ekit_2012.3.tgz

                               

                              calbr_perc_user.pdf

                               

                              calbr_solns_pv_user.pdf

                               

                              calbr_ver_user.pdf

                               

                              svrf_ur.pdf

                               

                               

                              Tung Yi is going through these manuals now and doing tests suggested from you.

                               

                              Here is one Tung Yi’s question:

                               

                              The following command suggested by you is used to define the voltage of the specific net:

                               

                              perc::define_net_voltage_by_placement

                               

                              It seems that the voltages and names of the nets assigned in the syntax require manual wok. For a large circuit, this effort would be tedious and strenuous. Is this normally done by C-shell kind of automation language or can be done by other method?  We have not learned C-shell yet.  Can you let us know how this can be done for a large circuit?

                               

                              We expect more questions to come on this subject as Tung Yi goes through the testing process.

                               

                              Here we have another question on Calibre commands on calculating metal area connected to the nodes (Gate, drain, source) of each of every transistors in a large circuit. 

                               

                              We find the command called “Net Area Ratio” which does only scanning through all transistors in the circuit and print the information about the ratio between the area of the metal connected to the node of the transistor and the node area (e.g., gate area or source/drain diff area which can be user defined) of the transistor.  However, the print-out information are not labeled with transistors, rather, they are associated with the coordinates of the locations where this command reports errors.  We know this command is DRC (Design rule checking) command, and it will allow us to print out the information only when DRC checking using this command fails.  So to extract the metal area information mentioned above, one way is to intentionally to make this DRC check command fail for all of the transistors in the circuit which will then allow us to print and extract the information we need for all the transistors in the circuit.  (i.e., area of the metal connected to the transistor node can be extracted by multiplying the reported ratio with the node area.)  The problem here, however, is that we want the extracted metal area to associate with each of every transistor in the circuit, i.e., labeled with transistor names, not the coordinates of the failed locations.  Yes and No, this seems to be something related to what you mentioned earlier to assign properties to polygons.  However, may not be quite the same.  Maybe you or someone on this forum knows the answer for this.  There may be other better ways other than we are doing now to achieve this.  If yes, we are eager to know them.

                               

                              Thank you very much for your assistance.

                               

                              Regards,

                               

                              Tom            

                              • 12. Re: Can identify the every MOS on layout with calibre tools/command?
                                dan_liddell

                                Hi Tom,

                                 

                                “ Is this normally done by C-shell kind of automation language or can be done by other method?  We have not learned C-shell yet.  Can you let us know how this can be done for a large circuit?”

                                 

                                Please see my May 9 posting earlier in this thread. There is a complete discussion there. You can learn csh if you wish, but Tcl will be more beneficial for you in the short term.

                                 

                                As far as finding polygonal areas you describe and writing them out, that seems more like a job for a layout editor tool than for a verification tool. Having said this, there may be some means to get it done in DRC. I’ve not done it myself. The operation for assigning property values is DFM Property.

                                 

                                dan

                                • 13. Re: Can identify the every MOS on layout with calibre tools/command?
                                  dan_liddell

                                  And after thinking about it a bit, you should be able to get your metal areas onto your devices using the LVS Annotate Devices (LAD) flow. Basically this involves the following:

                                   

                                  1. Derive your layers of interest. This may or may not be needed as a separate step from #2, depending on what the DFM Property NODAL keyword will get you.

                                  2. Use DFM Property to assign properties to a derived layer. In your case, you’ll probably be using the gate layer to assign  properties to. You’ll need the AREA() function in your property expression to get metal areas. The CONNECTED or NODAL keywords may prove useful.

                                  3. Use DEVICE LAYER with the ANNOTATE keyword. The section (linked in the SVRF Manual) that discusses the LAD built-in language will be useful.

                                  4. Use LVS Annotate Devices for the devices of interest.

                                   

                                  This flow will place the properties (areas in your case) on the device bodies. Then when you extract the devices, those properties show up in the SPICE netlist with the associated instances.

                                   

                                  Hope that helps.

                                   

                                  dan

                                  • 14. Re: Can identify the every MOS on layout with calibre tools/command?
                                    tungyi.cop00g

                                    hi, Dan

                                     

                                    I'm TungYi.

                                     

                                    when I used tcl to extract the information of the net, there's some problem that I can't figuare out to fix the bug.

                                     

                                    List it below:

                                     

                                    #1=========================================

                                    proc test {dev} {

                                    set testaa [perc:get_nets $dev –name G]

                                    }

                                     

                                    wrong # args : should be “test dev” 

                                    #2=========================================

                                     

                                    while used the command "perc::export_net" , the report said "invalid command name"

                                     

                                    By the way the version of my Calibre is 2012.2, the command perc::export_net is not in the Calibre_perc_user.pdf.

                                     

                                    Is this a new pakage of the command which can only be used at the new version of the Calibre? 

                                     

                                    #3=========================================

                                     

                                    Wrong arguments in calling perc::get_nets

                                     

                                    “perc:get_nets $dev –name G”

                                     

                                    Invoked frome within

                                     

                                    invalid command name

                                     

                                    ERROR:invalid command name “my proc name”

                                     

                                    No source code available error “called a copy of a compiled script”

                                    #4=========================================

                                    the command you suggest us to try list below, 

                                    ldl::export_perc

                                    ldl::select_nets

                                     

                                    there are not in the calibre_perc_user.pdf manual

                                     

                                    and how can I run the ldl:: command?

                                     

                                    Is it same as the perc:: which write at the .txt file?

                                    #5============================================

                                     

                                    Also the person which I ask to give me the QuickStart pakage said that the PERC LDL frame work seems

                                     

                                    like calibre_perc_user.pdf.

                                     

                                    But as I study this book, the book said the PERC LDL has other pdf file.

                                     

                                    So, the commands which I can not find in the manual you suggest are in the newer version of the Calibre, right?

                                     

                                    Or in the PERC LDL frame work?

                                    #6=============================================

                                    Also can you give me a simple example(only a mos or 3points of the nets) to

                                    extract the nets and voltage information?

                                    #7=============================================================

                                    here is my code of the TVF FUNCTION,

                                     

                                    most problems are mentioned #1~#4.

                                     

                                    I have no idea to debug it.

                                     

                                     

                                    TVF FUNCTION esd [/*

                                    package require CalibreLVS_PERC

                                    proc init {} {

                                     

                                        perc::define_net_type "Power"  VDD

                                        perc::define_net_type "Ground"  GND

                                     

                                        perc::define_net_type_by_device "Gate" -type MN -pin g -cell

                                        perc::define_net_type_by_device "SrcDrn" -type MN -pin {s d} -cell

                                        perc::define_net_type_by_device "Cap" -type C -pin {p n} -cell

                                     

                                     

                                        perc::create_net_path -type R

                                        perc::define_net_voltage_by_placement 1.0 \

                                        "VDD Gate"

                                     

                                    }

                                     

                                     

                                    proc check_HBM_diodes {} {

                                        perc::check_net  -netType {Power} -cellName lvsTop -condition demo_devgate_net \

                                               -comment "asdsadasdasdasdassasa"

                                    }

                                     

                                    proc qasd {} {

                                    set qyy 2

                                     

                                    }

                                     

                                     

                                    proc cond_HBM_diodes {net} {

                                        set up_diode_count   [perc::count -net $net -type D -pinAtNet {pos} -pinNetType {neg Power}]

                                        set down_diode_count [perc::count -net $net -type D -pinAtNet {neg} -pinNetType {pos Ground}]

                                        if { $up_diode_count == 0 || $down_diode_count == 0 } {

                                    # Missing expected diodes, report it as an error

                                    if { $up_diode_count == 0 } { perc::report_base_result -title "Missing up HBM diode" }

                                    if { $down_diode_count == 0 } { perc::report_base_result -title "Missing down HBM diode" }

                                    return 1

                                        }

                                        # Otherwise, this I/O net is OK

                                        return 0

                                    }

                                     

                                    proc demo_devgate_net {dev} {

                                    set gate_netItr [perc::get_nets $dev -name G]

                                     

                                    }

                                     

                                    puts "print message test"

                                     

                                    */]

                                    ===================================================

                                     

                                    Thanks lot.

                                     

                                    If there's someone can also help me to solve this problem, just telling me how can I do. Thanks.

                                     

                                    TungYi

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