The task is to extract node voltages (which appear in the netlist report after running SPICE) and then paste these voltage values on polygons (i.e., metal lines) in layouts. We then would like to achieve the goal of reporting the voltage difference between all adjacent metal lines into an output file.
What we have:
An schematic of a simple test circuit (Cadence format) constructed by one nmos transistor.
NETLIST file of the above schematic (generated by HSPICE or Spectre)
GDS file of the same circuit (generated from Cadence Virtuoso)