I have not seen that combination of symtoms before, but it sounds like a problem I would be able to help with. Here's something you could try if you like... You could go to SupportNet and open a Service Request (SR). You could copy/paste the problem from this thread and mention that Chris Balcom would like to participate in the debug if possible. I look forward to helping.
I had the same problem, welcome to all the changes you have to do with your rule files.
You will end up with a different set of rule files to use at top level versus intermediate levels.
The black box thing got me until I used: LVS NETLIST BOX CONTENTS NO
For the extra cells that are added, check the results of the *.sp file (calibre -spice creates the .sp file from the gds).
If you see a seed promotion, spend the time to find out why, it is probably losing a power connection somewhere.
LVS EXPAND SEED PROMOTIONS YES
You have to spend a lot of time massaging hcells, filter options, and lvs report options to get the top level right.
You have may have virtual connections with the colon :. At the top level, turn off all of those virtual connections
allowed at top level. For the hierarchy, use
LAYOUT RENAME TEXT "/://"
also check your source bus label nomenclature, versus the layout for busses
the following worked for me to bring the busses inline and match with other-
where the bus nomenclature from place and route of synthesized blocks were
different from the hand created schematic blocks
LAYOUT RENAME TEXT "/\\[/</g" "/\\]/>/g"