3 Replies Latest reply on Jun 10, 2013 1:22 AM by robert_davies

    netnames in busses of hierarchical designs


      Hi All,


      I did create a hierarchical block for a DDR3 memory. I then added the individual Data, control and address signals to busses. Those busses I intend to set to hierarchical ports. How can I make sure, that the signal order in the top level schematic bus is corresponding to signal order in the hierarchical block  schematics?