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netnames in busses of hierarchical designs

Question asked by Stone on Jun 7, 2013
Latest reply on Jun 10, 2013 by robert_davies

Hi All,

 

I did create a hierarchical block for a DDR3 memory. I then added the individual Data, control and address signals to busses. Those busses I intend to set to hierarchical ports. How can I make sure, that the signal order in the top level schematic bus is corresponding to signal order in the hierarchical block  schematics?

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