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Verilog A FACE models

Question asked by earnest_aruj on Jun 19, 2013
Latest reply on Aug 29, 2013 by earnest_aruj

Hi,

 

I'm doing signal integrity on a Processor based design.I have hyperlynx SI 8.2.1.

I got the models as Verilog A FACE models

 

Does hyperlynx support Verilog A models ?

 

 

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