5 Replies Latest reply on Aug 29, 2013 10:49 PM by earnest_aruj

    Verilog A FACE models

    earnest_aruj

      Hi,

       

      I'm doing signal integrity on a Processor based design.I have hyperlynx SI 8.2.1.

      I got the models as Verilog A FACE models

       

      Does hyperlynx support Verilog A models ?

       

       

      Earnest

        • 1. Re: Verilog A FACE models
          cristian.filip

          Hi Earnest,

           

          We have been successfully using those models since 2011 and here are our findings:

           

          • Eldo/ADMS in HyperLynx 8.2.1 does not support Verilog A even in HSpice compatible mode. HSpice is required as simulation engine to properly simulate with those models.

          • Although the documentation provided along with those models recommends using 2008.xx HSpice version or higher, we had issues when trying to make them work in 2010.xx versions, so we ended up to move to HSpice F-2011.09.

          • With some modifications the models can be used directly in LineSim (assign them through differential IC symbol). They properly run in FastEye Channel Analysis Wizard, but you need to manually characterize the channel using pulse and step waveforms. That means you will have to modify the stimulus file provided by vendor such as to be able to generate those waveforms.

          • We have recently experimented with HyperLynx v9.0 build 631456 (from May 2013) and haven’t been yet successful with those simulations. Moreover we are confused about how to enable HSpice as circuit simulator in this HL release from the Preferences Menu -> Circuit Simulators tab. On the previous HL versions toggling between Eldo/ADMS and HSpice used to be done thru a radio-button. This radio-button is not there anymore (see the attached screenshots), so we are not sure how to enable HSpice. Consequently it would be appreciated if someone can provide a solution to this issue.

           

          Hope this helps,

          Cristian

          1 of 1 people found this helpful
          • 2. Re: Verilog A FACE models
            steve_kaufer

            Hi Cristian (and All),

             

            Regarding Verilog-A simulation, some improvements have been made in HyperLynx v9.0. Someone has contacted you off-line to discuss details, and hopefully a summary conclusion will be posted to everyone soon.

             

            Regarding how to specify the use of HSPICE in v9.0, the controls have changed. I'll describe them in words here and attach a few pictures:

             

            - To change the simulator being used to HSPICE (or another choice) from the oscilloscope, pull down the combo box just below the Start Simulation button in the upper right corner. It defaults to "Auto" (meaning let HyperLynx choose automatically, based on assigned models), but you can override to your preferred choice (including HSPICE).

             

            - However, in v9.0, there are more places (than just the oscilloscope) where you might want to specifically select a simulator - for example, when using EZwave as a waveform viewer (instead of the oscilloscope), or for batch simulation. So the general way to choose is from Setup > Simulation Controls, which opens a dialog box new to v9.0. In it, at the top, select the "Fixed" radio button (meaning specify a fixed simulator choice), then select from the combo box.

             

            Regards,

             

            Steve Kaufer

            1 of 1 people found this helpful
            • 3. Re: Verilog A FACE models
              rocco_gruschwitz

              I've sucessfully used Verilog-A FASE models for Panther Point and Lynx Point in HL 8.2.1 and 9.0 without using HSpice. It was working fine.

               

              Regards

              Rocco

              • 4. Re: Verilog A FACE models
                cristian.filip

                Hi All,

                 

                After working with Mentor folks nearly a day, we figured out that ADMS does support Verilog-A FASE models and the results are consistent with those generated by HSpice. However the user needs to have full admin rights over the “work” directory and the associated sub-directories under the installation path:

                 

                C:/MentorGraphics/9.0HL/SDD_HOME/hyperlynx64/Ams/pkgs/icx_pro_mb/icxbase/VHDL-AMS/work 

                 

                In my case the directory was “read-only” preventing the compiler to generate the temporary files. That explains the error messages that I was getting.

                 

                Thanks to Mentor folks for their effort and exceptional support,

                 

                Cristian

                • 5. Re: Verilog A FACE models
                  earnest_aruj

                  Hi Cristian,

                   

                  Could you help me how to Simulate the verilog A FASE models.

                   

                  I'm able open and see the models(.inc file) in hyperlynx , but i'm not sure how to assign the required stimulus.

                   

                  I'm using Hyperlynx SI 8.2.1

                   

                  Regards,

                  Earnest