I'm doing signal integrity on a Processor based design.I have hyperlynx SI 8.2.1.
I got the models as Verilog A FACE models
Does hyperlynx support Verilog A models ?
We have been successfully using those models since 2011 and here are our findings:
Hope this helps,
Hi Cristian (and All),
Regarding Verilog-A simulation, some improvements have been made in HyperLynx v9.0. Someone has contacted you off-line to discuss details, and hopefully a summary conclusion will be posted to everyone soon.
Regarding how to specify the use of HSPICE in v9.0, the controls have changed. I'll describe them in words here and attach a few pictures:
- To change the simulator being used to HSPICE (or another choice) from the oscilloscope, pull down the combo box just below the Start Simulation button in the upper right corner. It defaults to "Auto" (meaning let HyperLynx choose automatically, based on assigned models), but you can override to your preferred choice (including HSPICE).
- However, in v9.0, there are more places (than just the oscilloscope) where you might want to specifically select a simulator - for example, when using EZwave as a waveform viewer (instead of the oscilloscope), or for batch simulation. So the general way to choose is from Setup > Simulation Controls, which opens a dialog box new to v9.0. In it, at the top, select the "Fixed" radio button (meaning specify a fixed simulator choice), then select from the combo box.
I've sucessfully used Verilog-A FASE models for Panther Point and Lynx Point in HL 8.2.1 and 9.0 without using HSpice. It was working fine.
After working with Mentor folks nearly a day, we figured out that ADMS does support Verilog-A FASE models and the results are consistent with those generated by HSpice. However the user needs to have full admin rights over the “work” directory and the associated sub-directories under the installation path:
In my case the directory was “read-only” preventing the compiler to generate the temporary files. That explains the error messages that I was getting.
Thanks to Mentor folks for their effort and exceptional support,
Could you help me how to Simulate the verilog A FASE models.
I'm able open and see the models(.inc file) in hyperlynx , but i'm not sure how to assign the required stimulus.
I'm using Hyperlynx SI 8.2.1
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