8 Replies Latest reply on Jul 31, 2013 2:37 PM by michael.weinberg

    How to join nets



           There is a PCB with AGND and GND nets on it, which were supposed to be joined somewhere on PCB. normally, I join them with a 0 Ohm resistor, which means I have to add an extra component, this doesn't look pretty. I was wondering if there is a solution in dxdesigner to maintain these two spearate net names and connect them together in PCB (maybe by some special component or something)


        • 1. Re: How to join nets

          I am using mentor EE7.9.4, by the way

          • 2. Re: How to join nets

            You can use "|" to alias Net names. If you rename GND net  as GND|AGND, now GND and AGND be same net



            • 3. Re: How to join nets


                   Glad to talk to you again, you are really a hard wroker, you should ask your boss for a pay raise, hah:)

                   Actually, my situation is a little complicated than you think. it's not just as easy as connecting two nets. I'll give you a detail description of my situation, then you will understand what I really want.

                   let's say, there are two engineers, Jim and Tony. Jim design the schematics and Tony do the layout. One day, Jim was asked to design a pcb with very sensitive analog compnents and aggressive digital Components on his PCB, so he decide to separate AGND and DGND, which could avoid the digital components from intefering the analog system.

                  if Jim  use the net alias "AGND|DGND", as you suggested. he will find this doesn't work, because with net alias,  dxdesigner just rename AGND to "AGND|DGND", expedition will take AGND and DGND as the same net.  Tony, the layout guy, could also connect the DGND pin of digital components onto analog ground plane, which is not supposed to be. this could be a disaster.

                   So, what Jim really want is to keep all analog components onto AGND plane, and all digital components onto DGND plane, any component with one GND pin(DGND or GND) can not be connected to the other ground plane. and also DGND and AGND could be connected somewhere on PCB. only in this way, Tony doesn't have a chance to connect an component from DGND plane to AGND plane.


                   I am not sure I explaned my idea clearly, so, if you don't mind, I'll type my quesiton in Chinese( I guess you are a Chinese).

                   我的情况是这样的,当两个工程师协同工作的时候(原理图工程师和Layout工程师)。如果一个PCB上同时出现了AGND和DGND两个信号情况会变得比较复杂。如果原理图工程师直接用Net Alias将两个网络连接起来会造成一些误解,因为在这种情况下Expedition会认为AGND和DGND是同一个网络,那么Layout工程师可能会在不知情的情况下降一个原本属于DGND的元件连接到了AGND平面上,因为expedition不会阻止这种走线方式。这种结果可能不是原理图工程师希望的。

                   所以,我认为一个比较合适的方法是,应当保持AGND 和DGND为两个独立的网络,这样子Layout工程师就不可能降DGND的元器件连接到AGND上边来了。当然,这种要求的麻烦之处就是用什么样的方式在一个合适的地方将AGND和DGND短接。

              • 4. Re: How to join nets



                Maybe this is an option to your issue.

                Create a buried resistor only make the distance between the towo pads zero (so they actuallty short)


                this is how to make the cell.


                The package group needs to be Buried! ,Package group - Embedded Resistor or Embedded Capacitor  do not exist


                These steps below give a step by step description how to do this for example for a buried resistor.

                To create a "buried resistor"...

                1. Create a 2 pin cell.
                  - Assign it the Package Group of "Buried".
                  - Enable "Plane Shapes" in Display Control and draw (place) a "Resistor Shape". The pads of the SMD Cell must overlap the resistor shape area.

                2. In Expedition PCB Setup Parameters>Buried Resistors & Rise Time dialog:
                  - Toggle on the "Allow buried resistors" option.
                  - Define the Layer Stack Center.



                1. In the Place Parts And Cells dialog, select the Active Layer and place the resistor.
                2. In the Gerber Output dialog, depending on the process used, do one of the following:
                  - Include "Resistor Areas" when processing the layer.
                  - Exclude "Resistor Areas" when processing the layer. Create an additional Output file and only include "Resistor Areas".

                Note: Once the buried resistor is placed, the Push command can be used to move it to different layers.

                Note: To be able to place parts on inner layers, cells must have Mount Type=Surface, use smd pads for all pins and must be in Package Group =
                "Buried". They do not have to have Placement Outlines because they are considered screened components.



                • 5. Re: How to join nets

                  it's common to short GND/DGAN on one location(point ground) for better interferecing control between digital partition and analog partition,caused by power/ground common mode noise. Alomost every  layout designer know how to do it properly, so don't worry about it. If you still having concerns that layout designer may forget to seperate GND and AGND and short it on one location, you can add a note on your schematics.


                  If you indeed a virtual shorting symbol be added in your schematics, just create that symbol ,cell and pdb entry. You requirement was discussed decades old and you can find same discussion on the community.



                  • 6. Re: How to join nets

                    hi wim,

                         I like your solution, it completely solved my problem.

                         a further question, I got a DRC error said the distance is not valid between resistor shapes, and I checked the package of my buried resistor, I found there are two resistor shapes overlapped together. Actually, I put only one resistor shape on the package.  I tried to delete the extra resistor shape, but after I saved the cell and re-open it, there still are two resistor shapes overlappe each other in the cell. maybe this is not a big deal, but i still want to know how to clear this DRC error, Thanks!

                    • 7. Re: How to join nets


                          Wim's solution is actually what I want, but I met some small difficulties in his solution, you might noticed in my last post. since I didn't get any response from him, I was wondering if you can cover my issue.

                           I build a buried resistor to short AGND and DGND, steps as follow

                           1. choose package group as buried, put two SMD pad in cell editor.


                                  Q. Why do I need 2 layers to edit a cell? i mean it's SMD, what is the othere layer used for?

                           2. draw a resistor shape to connect two pad.


                           3. enable buried resistor in "setup parapaters" dialog.


                           4. include resistor shape in gerber file generation .

                         everything works fine, except that I get a DRC error said the resistor shaped clearance is two small, and then I checked the buried resistor cell, I found there are two resistor shape overlapped together, which I am pretty sure I put only one resistor shape in the cell. I tried to delete the extra resistor shape, it doesn't help, after I close the cell enditor and reopen it, there still are two resistor shape overlapped together.

                           besides, I get another warning in message window everytime I start expedition,it's really strange, i suppose buried reisistor is a kind of embeded passives, why they can't be supported in the same design?



                         Hope you can help me out, thanks.

                      • 8. Re: How to join nets

                        I agree, buried resistors are embedded passives!


                        Perhaps the distinction made by Mentor is that embedded passives are used for capacitors (and maybe inductors as well). Does anyone use both embedded capacitors and resistors in the same layout?


                        Here's a related post of mine on the subject: http://communities.mentor.com/message/42534#42534.


                        I don't have an issue with the "false" DRC errors generated when connecting two nets as discussed in the referenced post, but I do take issue with the net assignment of the conductive shape changing after running Project Integration (a bug)!


                        Using an RF shape will avoid "false" DRC errors, so use this if you have a license for this option.