I was starting out actual layout of my circuit but started to face some issues with drc/lvs. So i had decided to do a simple inverter to make sure my calibre is using the right rule files for drc and lvs. Please find attached my inverter's schematic (sizing shown in the picture) and layout.I am using IBM 130nm PDK.
I have observed the following:
1. If I use the NW contact available during the instantitation of PMOS which attaches/abuts the NW contact along with the PMOS, my DRC is clean. Whereas if I dont use that option, its throwing me DRC errors[document attached for that] related to chipedge. Why is it so ?
2. I have also attached the LVS errors (document attached) which are same in both the cases - whether I use the automatic option of NW contact or drawn maunally. I am not able to figure out why this error comes even though the connections, source of pft/nfet and sizing everything is same in schematic and layout. The error says my instances are mismatched. I am using fingers in both schematic and layout.
3. A. I have one generic question- If we have many nfets in the schematic, should we use one subc symbol each for each nfet in schematics to pass the LVS or can we use just use one subc symbol and connect all sources and bulk to it.
B. From the perspective of lvs, is it advisable to use the automatic option of subc contact available in the PDK for layout or manually draw it ?