In my full chip design I have multiple IO pad groups, one regular IO, 2 pairs of Oscillator IO with their corresponding supplies, A pair of analog VD, VS Pad. The VSSIO ring is common to all these pads for ESD purpose. The VDDIO, VDD, VSS power rail for each group were given different names ( like VDD1, VDD2, VDDIO1 etc). In LVS the connectivity is not matched. The FX mismatch says that the particualr power nets of each IO pads are connected to some nets with different numbers ( 3456 etc) instead of VDD1 or VDDIO1 or VSSIO). I can see that both the layout and source has the nets, but the layout names corrsponds to some numbers rather than the net name. How can I solve this?
Also there are ESD diodes for all these Pads which is being reported as unmatched instance. Please help me solve the issue.
thanks
Gopakumar
Hi Gopakumar,
Is the circuit extraction report (.ext file) clean? Any shorts, opens, or bad devices?
As far as the instance mismatches go, it sounds like you have devices not being recognized in the layout. If the circuit extraction report shows BAD DEVICE errors, that may show the problem directly. If not, I would check the DEVICE statements in the rule file to ensure they cover the devices you need. Pay particular attention to the pin and seed layers. Ensure they are derived correctly and that the pin layers have connectivity in the CONNECT set and the layer derivation tree.
The rule file analyzer (calibre -svrf rules) can sometimes help with CONNECT and DEVICE issues. Use the HELP command to see a list of interface commands.
The unmatched diode instances might have something to do with the LVS errors you mention. You may not be getting the connectivity you expect across the diodes if they are not recognized.
If your connectivity text (TEXT LAYER) has been properly specified and attached, you should see your top-level nets get extracted with names. If that's not happening, check your TEXT LAYER statements and the method you use to attach those lables to nets.
dan