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Tombstoning and skewing, of a small chip component, is caused by unequal wetting of the two terminals. This may be the result of:
Incorrect land patterns - use IPC7351 standard
Thickness of Soldermask - make sure the mask is below the level of the lands
The lack of or imbalance of thermal relief's
Thickness of the Solderpaste - may need to adjust the stencil apertures
The reflow profile may need adjusting to allow for thermal load
Pick and Place machine inaccuracy - one end of the SMD is being placed off the land
Thank you very much for the explanation. I think this helps everyone understand some of the causes for Tombstoning.
Now, what are you and other customers doing within PCB layout to prevent "lack or imbalanced thermal reliefs"? I know some customers simply do not allow plane thermals on these devices and force connections through traces. Are there any methodologies specific to pad entry or trace thickness that can be used in layout to aid the prevention TombStoning?
as PCB designer you only can guess what would be best to get rid of Tombstoning.
But close contact to your PCB assembly is one of the keys here.
To control the effect, you have to look after symmetric soldering process on both sides of the component.
We see two areas where you can do this. One is (symmetric) pad, entry the other is solder paste optimization.
The first one you can easily check by automation scripting. The otehr one has to be managed or driven by your PCB assembly.
Thanks everyone for the responses. Looks like prevention of TombStoning is best done by understanding the manufacturing causes and incorporate solutions into the land patterns and soldermask and paste thicknesses.
On the Layout side it seems the best practice is to ensure balanced thermal reliefs. Validation of balanced thermal reliefs can be easily done via automation scripts during the layout process.
One other thing to possibly add is the removal of solder resist from under the smaller (0201) components?
This is a relatively safe thing to do as there is no way copper flooding will be able to get between these pads. (plane keep out built into the component will also prevent this).
There is a potentially small sliver of resist that could create an imbalance if the resist is slightly proud.
With assembly houses reducing the thickness of paste (usually 100u, now reducing to 75u) due to the size of smaller lands for BGAs & 0201 components, this is having a much larger effect on tombstoning as there isn't a 'surplus' of paste to prevent the tombstone occurring.
Add to the fact that Pb-free paste also is nowhere near as 'strong' as Pb paste then all you need to have is a small difference in temperature during the assembly process to create this problem.
Another key to avoiding/minimizing tombstoning and other solder related defects is to use automated rules to generate your solder stencil aperatures directly from the land pattern information. Typically, manufacturers have pretty robust guidelines for stencil apreatures, but the disconnect is in the actual fabrication of the stencil. The stencil vendor must manually edit Gerber data to modify it to comply with the manufacturing guidelines. This works most of the time, but as with any manual process, it is error prone. One alternative is to use the CAMCAD Stencil Generator, which allows you to define what type of apperature you need per land pattern and then automatically apply these rules to your board to create the actual stencil for manufacturing. Customers that have taken this approach have reduced their in-process solder defects by more than 50%. Using this type of tool along with the design time improvements you mention will significantly improve manufacturing yields.