Hello PCB Designers,
I would like to get some information on how users are preventing PCB designs from having possible problems with TombStoning during manufacturing. I understand that validation can be done as a post process to layout using DFF type batch validation; however what are some methodologies that are being used to prevent these problems during the layout of the PCB design? Here are some additional questions to help me understand the mythologies used to prevent TombStoning during PCB Layout.
Do these prevention methodologies have to be modified specific to the manufacturer being used for the design?
How are plane connections handled to prevent TombStoning?
Are symmetric connections to each side of these small chip devices critical to the prevention of TombStoning?
Does the trace width itself need to be altered as it enters the small chip device in prevention of TombStoning?
Any information that can be provided will be useful to understand how automated methodologies could be incorporated into PCB Layout to prevent Tombstoning earlier in the design process.
ExpeditionPCB/XtremePCB Product Marketing Manager