Cellmap file and split busses

Discussion created by gabriel.bertotti on Oct 8, 2013

    Hallo everybody,


i'd really appreciate if anybody could give me his opinion about my following problem:

I'm trying to make a post-layout simulation of the interconnections of a Mixed-Signal ASIC

(actually I'm focusing on only one net - over which I expect and I'd like to estimate an important voltage drop).

so I'm doing a Gate-Level extraction with hcell and xcells and everything works fine as long as

I don't generate a calibre view for cadence virtuoso.


My PEX netlist looks ALWAYS fine but:

     1) If my h/xcells are the top-hierarchy cells it happens that one of them is not recognized, althought it is mapped in the cellmap file and thus the generation fails.

     2) If I use h/xcells of another hierarchical level I got that a cell "A" with bus outputs cannot be properly connected, althought other cells with bus outputs don't show

     any problem. The only difference is that this bus output of "A" is split to drive single transistor/subcells.

     However I can get a correct calibre view if I use as h/xcells the subcells of "A", which also have bus outputs, which then drive again single transistors/subcells.


Have all these weird behaviors of the calibreview generation script anything in common? Or could any of you have any idea where i could find any hint about this problem?


Thanks in advance for reading,


best regards