5 Replies Latest reply on Oct 10, 2013 5:27 AM by robert_davies

    Creating and modifying blocks and schematic sheets in hierarchical designs

    alex.ballantyne

      Hi,

       

      We have completed a large hierarchical schematic but have been frustrated by some of the things that happen in DxD when creating blocks and editing the schematic sheets that lie beneath.

       

      I'm hoping someone here can offer some help and advice so that we can use DxD more effectively for this kind of schematic.

       

      We have had to work by manualy adding pins to frozen block symbols and hierarchical connectors to schematics individually because of the behaviour of the features that should assist with these tasks in DxD.

       

      The design was done in 7.9.3 but I have confirmed these issues exist in 7.9.5 too.

       

      Connecting pins on blocks that are not "frozen"

       

      For example, suppose you have created two blocks (using Add/Block) located on a sheet that will be at the top of the schematic hierarchy.

      Each block has been edited to add a pin, "OUT1" on the left block and "IN1" on the right block.

      If these blocks are conneted by a net, all is well until the net is named. Suppose the net is named "SIGNAL". Now both pins will have their names changed to "SIGNAL", which is not what I want bcause the pins are intended to connect to nets called OUT1 and IN1 in the left and right blocks respectively. No warning is issued, there is no confirmation dialogue. If a signal is deleted, so are any pins attached to it.

       

      Is this the intended behaviour of DxD? Is there some way of controlling this other that freezing/unfreezing the blocks (which has other consequences).

       

      Traversing the hierarchy when blocks and schematics are incomplete.

       

      Suppose the schematic is a work in progress. If you push into a block which has a missing pin, a dialogue is presented offering the option of deleting the "extra" port(s) for the schematic. No information is provided to suggest which port is un-matched to a pin. Running Verify doesn't provide any clues either. Manual checking pins to ports seems to be the only way to resolve this which is time consuming and frustrating since DxD clearly has identified the error.

       

      Adding Missing Pins

       

      Now suppose that on the sheet with mismatched ports we now do Generate Symbol and select the "Update It" option and check the Open in Symbol Editor option.

      We are presented with a symbol with the missing pins added but now all the pins have moved to the default locations and have been changed to IN/LEFT. That's not what I've got in mind for an "Update". This isn't really any use other than for initial symbol creation since adding a single pin requires all the pins to be re-positioned.

       

      Perhaps there is somthing we are missing here, and any help or advice would be welcome. We have the impression that DxD doesn't handle the creation and maintenance of hierarchial well and are reluctant to use it for future work of that nature as a result.

       

      Thanks,

       

      Alex.

        • 1. Re: Creating and modifying blocks and schematic sheets in hierarchical designs
          robert_davies

          Alex,

          You raise some valid points here, unfortunately much of what you have encountered is how DxDesigner is currently designed to work. There are a number of things you can do to mitigate the issues but you will not eliminate some of these limitations entirely.

          Fixing the pin name on a block is only possible by using the 'Freeze' option and, as you say, this is not ideal because of the consequences of unfreezing the symbol later. We are well aware of this limitation and intend to improve the functionality when we can get engineering time assigned to this particular aspect.

           

          It is not advisable to use the 'Generate Symbol' command to update pins added at the lower level of the symbol, add them in the symbol editor so that your existing changes are maintained This is a bit more laborious as you have to know what you've added and which pins have been removed. Any mismatch will be reported when you try and package the design to assist in clearing up any missing pins.

          For pins/ports that are removed automatically, these are reported in a log file that should also be seen in the Output window, you can open the log file from the File Viewer toolbar button. If you don't use the automatic update then you can investigate missing pins by using the Add - Missing Ports dialog, this will list ports at the higher level and show whether they've been instantiated in the lower level schematic. If you are making lots of changes then it might be worth switching off the automatic options and use the Missing Ports dialog instead.

           

          Finally you might like to vote for Ideas D3953 and D1587 these cover two aspects of hierarchical block management we will group them along with the other issues surrounding the current lack of functionality.

          Regards,

          Rob

          • 2. Re: Creating and modifying blocks and schematic sheets in hierarchical designs
            alex.ballantyne

            Hi Robert,

             

            Thank you for your prompt and full reply. Very helpful.

            You've confirmed what we thought; that this is DxD expected behaviour, all of which can be worked with once you realise what's happening.

             

            The Add/MIssing Ports dialogue works well and I can imagine we would use that in future designs.

             

            Can you clarify what you mean by "package the design" in this case, please? We don't have a Tools/Package menu pick (even though the DxD User Guide assures us that we should....) so I assume that all happens within the Tools/PCB Interface function. Pin/Port mismatches do get reported at that point, but it would be convenient to be able to generate a report without having to wade through the forrest of errors and warnings that result from running the PCB Interface on an incomplete design!

             

            Thanks for pointing out D3953 and D1587, off to vote now....

             

            Thanks,

             

            Alex.

            • 3. Re: Creating and modifying blocks and schematic sheets in hierarchical designs
              robert_davies

              You say you've tested this in 7.9.3 and 7.9.5 so I assume you are using the Expedition flow, in which case there is a Tools - Package option and a tool bar button. It is a process called the flattener that does the check prior to actually packing and assigning reference designators, and it will list mis-matches between the block and underlying schematic.

              If using PADS or some other layout tool then it doesn't look like the mismatch is reported in the same way.

              • 4. Re: Creating and modifying blocks and schematic sheets in hierarchical designs
                alex.ballantyne

                Hi Robert,

                 

                We are currently using  IND7.9.5_SW "Vendor Independent Flow" and there is no Tools/Package option on the menu and the Package button is greyed out.

                We previously used EE7.9.3 "Expedition Enterprise Flow" so I just fired that up to check and there is no Tools/Package option on the menu and the Package button is greyed out in that case too.

                 

                We see the mismatch errors when we run the PCB Interface to update the references but it's a bit late in the day by then.

                 

                Cheers,

                 

                Alex.

                • 5. Re: Creating and modifying blocks and schematic sheets in hierarchical designs
                  robert_davies

                  The package option will be available if the project is an Expedition Enterprise project as opposed to Netlist (Independent) which is why you see the same behaviour in EE 7.9.3. Packager is the Expedition executable, which is different to the PCB Interface executable.