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Increase the simulation time for FAST EYE channel characterization

Question asked by earnest_aruj on Oct 22, 2013
Latest reply on Oct 22, 2013 by Ed Bartlett

Hi,

 

 

I'm trying to simulate a PCIe gen 2 (5 Gbps) link in Hyperlynx SI 8.2.1

 

My required path is : FPGA-->connector--> 3 m cable --> connector --> FPGA

 

I'm not able to get any Pulse or Step response during FAST EYE characterization for 5Gbps if i add the 3m PCIe cable (part no: molex #74546-0403)  to my path, The simulation time is only 10nS (ELDO is used as simulator)

 

 

 

I'm able to get the normal oscilloscope eye diagram output

 

Connector and cable i'm using s parameter models and FPGA i'm using IBIS AMI models

 

 

Could someone help me resolve this issue ?

 

Will i get output if i increase the simulation time ? If so could someone help me how to do that ?

 

Regards,

Earnest

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