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Numerous power supply

Question asked by milostnik on Nov 19, 2013
Latest reply on Nov 20, 2013 by jduquette

Hello folks,

 

Our engineers have a question.

 

In a reference design they have multiple power supply attached to chips.

They have named the power supply with a the name of the used voltage and the name of the funcional bolock.

Example could be VCC_3.3V_Fiber or SMI_3.3V or plain 3.3V

Now in the power supply generation all this different power supplys are tighed together like the example picture attached.

 

In Expedition and DxD has no concept of starpoint and net connects (except for the unfortunate pipe that binds a maximum of two nets together)

 

The only official solution is to rename the power supply all to the same name e.g. 3.3V. This is in DxD easy.

 

But once done if the same schematic is used in another design and using unformal design reuse, you copy this part of the schematic to the new schematic. Then when you need to rename the power supply of this part of the logic, you hardly can select just the net names (e.g. 3.3V), becasue the names of the power supply you want to rename are the same with other power supply in the schematic, in this example evrything is 3.3V. So you have to tediously go from one net to the other, disconnect them, rename, and reconnect them. If you would have had the previous net names of SMI_3.3V, you could have renamed then to e.g. SMI_2.8V, and in the power supply section attached the new net name to a new source.

 

Is there any solution to this case?

Is there any way to put net names in a schematic together with one main net name, but keep them separate for handling and renaming?

 

In layout you would want some of the power supply net segment to have different trace widths.

 

In EE PCB there are no start points that are linked together with the net names indicated above. If you have only a smal set of power distribution trees, you could use minimal trace widths and normal trace widths. But this usage fails if you need more trees.

 

Does anyone know a good workaround for this situation?

 

I would really dream of having EE and DxD work so together that star point are inserted in the schematic. Every branch of the star point would have its net name and its own constraints, that are availble in Layout.

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