is anyone having experience with formal and informal re-use within Expedition Enterprise?
what about the constraints, are they maintained within the re-use block?
+what if there are conflicting constraints when the re-use block is instantiated in a new pcb?+
+how does packager cope with re-use blocks? Is there a way of working to maintain the data, such as reference designators, for the re-use block? (after all if we apply a re-use block we'd like to re-use the particular partslist, including reference designators, of this block as well)+
+you can imagine in a re-use block there are traces running through that block which are actually not connected to any parts (cells) in that block. We call them passing-through signals. Recently i did some concept study with formal re-use and found out that those traces disappear. This is not what we want. It can be that for instance a PCI bus (where we have some signal ordering to minimize crosstalk etc...) runs through that block and we don't want to re-layout the bus again.+
At the User2User conference there is a technical session by Terry Lovell about Formal Design Re-Use. If anyone is participating this session? I'd be greatfull if you share the details in this community.
Thanks in advance,