7 Replies Latest reply on Dec 3, 2008 9:09 AM by Jerry_Suiter

    Formal and Informal reuse within Expedition

    pascal_pardo

      Hi,

       

      is anyone having experience with formal and informal re-use within Expedition Enterprise?

       

      what about the constraints, are they maintained within the re-use block?
      +what if there are conflicting constraints when the re-use block is instantiated in a new pcb?+
      +how does packager cope with re-use blocks? Is there a way of working to maintain the data, such as reference designators, for the re-use block? (after all if we apply a re-use block we'd like to re-use the particular partslist, including reference designators, of this block as well)+
      +you can imagine in a re-use block there are traces running through that block which are actually not connected to any parts (cells) in that block. We call them passing-through signals. Recently i did some concept study with formal re-use and found out that those traces disappear. This is not what we want. It can be that for instance a PCI bus (where we have some signal ordering to minimize crosstalk etc...)  runs through that block and we don't want to re-layout the bus again.+

      At the User2User conference there is a technical session by Terry Lovell about Formal Design Re-Use. If anyone is participating this session? I'd be greatfull if you share the details in this community.

       

      Thanks in advance,

      Pascal

        • 1. Re: Formal and Informal reuse within Expedition
          terry_lovell

           

          Hi Pascal,

           

           

          Sorry for the late response, preparing for my U2U workshops, as you noted!

           

           

          The constraints are maintained within the RB when instantiated into a Host design only if the constraint class name (i.e.,Match_Group) is unique, that is, it doesn't already exist within Host design. If the constraint class name is unique, the constraint class will be automatically written into CES within the Host design and prefixed by the RB name (i.e., ROM8_Match_Group). If conflicting constraint class names exist in the RB and Host design (i.e.,Clock), no additional constraint classes are created in the Host design during instantiation and the constraint rules defined within the Host design take precedence.

           

           

          When instantiating a RB into DxDesigner, there are multiple options to control reference designators (i.e., Renumber as Needed, Renumber From, Add Suffix & Add Prefix) within the RB. Unfortunately I have not found a way to retain the original reference designators within the RB. If the reference designator within the RB is unique to the design, I would suspect that the "Renumber As Needed" would not change the reference designators upon packaging, but instead I have found that packager automatically prefix's a "1_" to every ref des in the first occurrence of the RB that is placed, and if duplicate RB's are place, "2_", "3_", etc. I will continue to test this and if I happen upon a solution, I will post it up to this forum.

           

           

          You are correct on the "pass-through" signals, unless the signal has an associated pin within the RB, netload will remove the signal. Think of a RB as a small contained design saved in the Central Library, if the signal doesn't exist in the schematic, it can not exist in the layout. A better choice may be "informal reuse" for this case, using the Circuit Move & Copy command. I hope this clears up any questions that you may have had concerning Formal Reuse.

           

           

          Thank you,

           

           

          Terry

           

           

          1 of 1 people found this helpful
          • 2. Re: Formal and Informal reuse within Expedition
            pascal_pardo

            Hi Terry,

             

            thanks for the clear feedback!

             

            I've one more question (as a matter of fact I'm sure i still have a lot of questions ) with respect to the passing-through signals. Per today in our customized way of working (in BoardStation) we're using so called interface ports. So for each passing through signal we have at least 2 interface ports which are in fact 1-pin components having a very small copper spot that needs to be instantiated on the board. This is kind of overhead of which i'd like to get rid of. Is there in DxDesigner/Expedition enterprise a possibility to use a kind of virtual interface ports. Defining a pin to the hierarchical symbol but in fact the pin doesn't need to be instantiated to the board, in other wordt it's not a physical pin. The only function would be that the passing-through signal is known/recognized in the reuse block. Hope you understand my question.

             

             

            Best regards,

             

             

            Pascal

            • 3. Re: Formal and Informal reuse within Expedition
              terry_lovell

               

              Hi Pascal,

               

              After reading your last post it sparked a few ideas that I experimented with. In the EE Flow we do in fact have Virtual Point (VP) capabilities that can be defined on "Complex" net topologies within the Constraint Editor System (CES). I first attempted to place a few interface ports (i.e., IN & OUT) within the schematic assigning net names to each (i.e., PASS_THRU_1, PASS_THRU_2, etc.), these are needed to create the external connections on the RB symbol only, no physical parts associated with these symbols. As I entered CES, the nets were recognized but displayed that there were zero "0" pins associated with these nets. I then was able to modify the topology of these nets to a "Complex" state, but as I entered the Order Netline dialog to define the VP's, all functionality was disabled. Thus, it appears that at least one (1) physical pin part must exist on a active net before a VP can be assigned to this net.

               

               

              Unfortunately it appears that the "pass through" nets must be defined in the EE Flow RB as you are presently doing it in the BoardStation design flow.

               

               

              Best Regards,

               

               

              Terry

               

               

              • 4. Re: Formal and Informal reuse within Expedition
                yu.yanfeng

                 

                We use Keyin flow, so We only use informal reuse within Expedtionpcb. Informa reuse is very flexible and save us lot of times. However, Reuse isn't supported in Xtremepcb mode.

                 

                 

                 

                 

                 

                • 5. Re: Formal and Informal reuse within Expedition
                  Jerry_Suiter

                  Hello,

                   

                   

                  Copy Move Circuit is supported within Xtreme PCB allowing users to copy between a design and paste within an Xtreme PCB Client.  If Cells or Padstacks need to be added to the Xtreme Session, we will start an interrupt process to ensure these library objects are replicated to all Xtreme PCB Clients. 

                   

                   

                  Currently Copy Move Circuit "Multiple Clipboard" is not allowed in Xtreme PCB at this time.  We have plans to add this as well as many other features next year.  Let me provide a summary of what we done specific to Xtreme PCB so far this year:

                   

                  In 2007.2 we have added full CES concurrent constraint entry within Xtreme PCB.

                   

                  In 2007.3 we have added the following Expedition PCB features within Xtreme PCB:

                  • Place->Board Outline

                  • Place->Copper Balancing Shape

                  • Place->DRC Window

                  • Place->Room

                  • Place->Route Border

                  • Place->Route Fence

                  • Place->Fiducial

                  • Place->Mtg Hole

                  • File->New Script Form

                  • File->Open Script Form

                  • Route->Swap Diff Pairs

                   

                  We also added a new feature called Sandboxes to both Xtreme PCB and Expedition PCB.  This functionality allows the user to do advanced protection of circuits by user handle as well as enables Auto Routing within individual Xtreme Clients.

                   

                   

                   

                  In 2007.4 we will be delivering concurrent Dimensioning support within Xtreme PCB.

                   

                   

                  Regards,

                   

                   

                  Jerry Suiter

                  Product Marketing Manager

                  Expedition PCB / Xtreme PCB

                  • 6. Re: Formal and Informal reuse within Expedition
                    yu.yanfeng

                    Hi Jerry,

                     

                    It's very important to support copying circuit from a layout library in Xtremepcb session. Imagin this case,You can save any partion of your layout into the layout library and share it with your collegues, everyone in Xtremepcb session can copy those layout from the library.It really saving time! Compared to formal reuse, informal reuse is flexible and convinient to designer. Hope Mentor add this capability a.s.a.p.

                     

                     

                    I also wish the Sandbox can support to allow mutilple persons to edit. This provide a mechanism to let every layout guys in Xtremepcb session can do work globally while preventing electrical engineer who joining to session to interface the work. As you known, Electrical engineer isn't so familiar with Expeditionpcb but he/she prefer use Expedtionpcb to join the session instead of using PCB viewer/browser.

                     

                     

                    Yanfeng

                    • 7. Re: Formal and Informal reuse within Expedition
                      Jerry_Suiter

                      Hello,

                       

                       

                      I agree that CMC is very important to the overall layout design process allowing quick informal reuse of physical layout already done in previous designs.  This combine with the Xtreme PCB technology is a real enabler in reducing design cycle times. 

                       

                       

                      I have some very good news about your CMC request.  I was able to do some research and determined we could enable Mutli-Board CMC within Xtreme PCB for the 2007.5 release.

                       

                       

                       

                      Regards,

                       

                      Jerry Suiter

                      Product Marketing Manager

                      Expedition PCB / Xtreme PCB