I am using Hyperlynx 8.2.1 for DDR2 batch simulation.In order to calculate the timing margin by considering the flight time,test load has to be mentioned in ibis file.
The ibis files have test load details. After the post layout simulation I got the timing margins.
I edited the test load values (changed the cref value), again i simulated. But results are same. How can the timing margins be same for different test loads?
How to resolve this? Is the flight time compensation taken care in DDRx Wizard? I am able to see this option in Generic batch wizard but not in DDRx wizard.
Please guide me with proper procedure to calculate the timing margin more accurately using DDRx wizard in Hyperlynx 8.2.1.
As per the following link (Technote : MG582097)
“Compensate signal launch skews to account for variations in time-to-Vmeasure” option is available in 9.0 version. Will this option solve the issue and gives us the accurate timing margins?