5 Replies Latest reply on Feb 11, 2014 10:59 AM by karen_chow

    Problems of post-layout simulation using Calibre LVS/PEX

    yi.luo

      Hi all:

       

      I'm facing a problem about the Calibre LVS/PEX, I will describe it using  this simple current mirror shown below, X and Y are same MOSFETs with  width=16, nfing=2, m=1:

       

       

      1.png

       

       

      When I just do the layout with only one finger for both X and Y (w=16,  nfing=1, m=1), and do the post-layout simulation, I injected 100uA to  node

      Vb, it has no problem seen from the post-layout schematic: X will absorb 100uA and Y will source 100uA.

       

      But when I use 2 fingers, the problem comes. The layout is:

       

       

      2.png

       

       

      In this layout, the X and Y are in a single transistor which has w=32  and nfing=4,  that means, X/Y are w=16, nfing=2 which is the same with  the schematic above. ------ This is in my mind what is correct.

       

      But when we do the LVS, it failed and showed property errors that X/Y  has 2 fingers in the schematic but has 4 fingers in the layout:

       

       

       

      3.png

       

       

       

       

      If change some MOS properties in the schematic, nfing is changed from 2  to 4 (layout doesn't change), then hen the LVS passes, which we think is  not correct (but it passes!). I used this extracted CalibreView file to  do the post-layout simulation, the current reduced to a half as seen  the comparison below:

       

       

      Pre-simulation, both X and Y have 100uA current:

       

       

      7.png

       

       

      Post-simulation, the current reduced to only 50uA:

       

       

      8.png

       

       

       

       

       

      Does anybody know what would be the problem is and give some help? Thank  you SO MUCH for any suggestions cuz I've been on this problem for days.  Thank you!

        • 1. Re: Problems of post-layout simulation using Calibre LVS/PEX
          yi.luo

          Here is some more information about the netlist. Anyone can help? Thanks a lot in advance!

           

           

          The netlist of the schematic is:

          ==============================

          ==========
          .SUBCKT test A GND Vb

            *.PININFO A:B GND:B Vb:B

            MM1 Vb Vb GND GND nsvtlp_rf w=16.0 l=0.5 nfing=2 srcefirst=0 ngcon=2 m=1
                     + mult=1 ncrsd=1

            MM2 A Vb GND GND nsvtlp_rf w=16.0 l=0.5 nfing=2 srcefirst=0 ngcon=2 m=1 mult=1
                     + ncrsd=1

            .ENDS
          ========================================


          and the netlist of the extracted layout (only for the MOSFETs):
          =========================================
          .SUBCKT test Vb GND A

                     ** N=259 EP=3 IP=0 FDC=4

                     M0 Vb Vb GND GND nsvtlp_rf L=0.5 W=32 nfing=4 ngcon=2 mult=0.25 ncrsd=1 $X=17420 $Y=-12305 $D=262
                     M1 A Vb GND GND nsvtlp_rf L=0.5 W=32 nfing=4 ngcon=2 mult=0.25 ncrsd=1 $X=18120 $Y=-12305 $D=262
                     M2 A Vb GND GND nsvtlp_rf L=0.5 W=32 nfing=4 ngcon=2 mult=0.25 ncrsd=1 $X=18820 $Y=-12305 $D=262
                     M3 Vb Vb GND GND nsvtlp_rf L=0.5 W=32 nfing=4 ngcon=2 mult=0.25 ncrsd=1 $X=19520 $Y=-12305 $D=262
              .ENDS

          =========================================

           

           

          It looks like the tool only considers one single MOSFET in the layout. In our LVS rules file, we have set:

           

             LVS REDUCE SERIES MOS                  NO
              LVS REDUCE PARALLEL MOS                NO
             LVS REDUCE SEMI SERIES MOS             NO
             LVS REDUCE SPLIT GATES                 NO
             LVS REDUCE PARALLEL BIPOLAR            NO
             LVS REDUCE SERIES CAPACITORS           NO
              LVS REDUCE PARALLEL CAPACITORS         NO
             LVS REDUCE SERIES RESISTORS            NO
             LVS REDUCE PARALLEL RESISTORS          NO
             LVS REDUCE PARALLEL DIODES             NO

           

          But the error is still there.

          • 2. Re: Problems of post-layout simulation using Calibre LVS/PEX
            dan_liddell

            One thing that may help is to turn on parallel MOS reduction. That way M0 and M3, and M1 and M2 in the layout will be reduced to two devices total, which is what you show in the source. But it seems the Device property computations for the layout may need some work also.

             

            LVS SPICE WRITE LAYOUT NETLIST and LVS SOURCE WRITE LAYOUT NETLIST can be helpful to see what LVS is comparing when doing reduction transformations and so on.

             

            dan

            • 3. Re: Problems of post-layout simulation using Calibre LVS/PEX
              yi.luo

              Thank you Dan! Could you kindly to show how to use these command lines to check what LVS is comparing?

               

              I made the parallel MOS reduction ON, but the problem is still there.

               

              Take a simpler example, if just put two NMOS transistors in the schematic and they are parallel connected (g-g, d-d, s-s-GND), each of which is W=3, L=1, nfing=1.

              In the layout, I put one transistor with W=6, L=1, nfing=2. The LVS width comparison is matched, but there's a discrepancy showing the property errors:

               

              Layout:  nfing=2

              Source: nfing=1

               

              and it does do the parallel reduction:

               

              =============================

              o Statistics:

               

                 2 layout mos transistors were reduced to 1.

                   1 mos transistor was deleted by parallel reduction.

                 2 source mos transistors were reduced to 1.

                   1 mos transistor was deleted by parallel reduction.

              ==============================

               

              But the LVS always can't be matched.

               

              Could you give more details about how to debuging this problem? Thank you in advance Dan!

               

              Yi

              • 4. Re: Problems of post-layout simulation using Calibre LVS/PEX
                dan_liddell

                Hi Yi,

                 

                I haven't had a chance to run your netlists through LVS. What I can give here is some general debugging advice.

                 

                1. Determine if the property values coming from the DEVICE statement's property computation block are reasonable. This isn't always easy to do without also looking at what the device reduction statement is doing (more on this below). But, if you already know the property values extracted by DEVICE are wrong, then you should begin debugging there.

                 

                Try to determine if the DEVICE property computation program is doing things correctly. If not, you may need to adjust that program. If the program is correct, you may need to make corrections to the pin layer derivations for your transistor. This can be tricky if DFM Property is involved in counting fingers.

                 

                2. Set the following in your LVS comparison rules:

                 

                LAYOUT PRIMARY parent_cell_of_bad_device

                SOURCE PRIMARY parent_cell_of_bad_device

                LVS REDUCE PARALLEL MOS YES

                 

                This is simply to reduce the data set.

                 

                Also set the two LVS specification statements I mentioned in my previous mail. If you have questions about these, look in the SVRF Manual.

                 

                3. Run LVS comparison. Then look at the two netlists that those two LVS statements generate. These will show the reduced property values for reduced devices. Check if the property values are reasonable for reduction.

                 

                LVS doesn't calculate reduced properties for built-in MOS devices except for L and W by default. For other properties like "nfing", you have to provide a reduction program in the LVS REDUCE statement (If you provide a reduction program, that program must calculate reductions for ALL traced properties, including L and W.) If your reduction of property values is not occurring properly, you may need to change the reduction program in the LVS REDUCE statement.

                 

                If you are confident the reduction program is correct, then you are back to either changing the DEVICE property computation and/or the derivation of the pin layers for the device.

                 

                Details for property computation and reduction programs are in Chapter 5 of the SVRF Manual.

                 

                dan

                • 5. Re: Problems of post-layout simulation using Calibre LVS/PEX
                  karen_chow

                  Hi! In calibreview setup window, you should use:

                  Reset properties: nfing=4

                   

                  Or if you are running batch mode, you should use either the schematiconly or sourcebased keywords:

                   

                  PEX NETLIST SOURCEBASED

                  OR

                  PEX NETLIST SCHEMATICONLY